ICM7556 Datasheet, PDF (5/11 Pages) Intersil Corporation – Precision Timing Pulse Generation Sequential Timing Time Delay Generation Pulse Width Modulation Missing Pulse Detector

ICM7555, ICM7556
1
2
OUTPUT
3
V_DD
4
V_DD
R_A
8
7
6
R_B
5
C
OPTIONAL
CAPACITOR
FIGURE 2B. ALTERNATE ASTABLE CONFIGURATION
OUTPUT DRIVE CAPABILITY
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the output swing at all supply
voltages will equal the supply voltage. At a supply voltage of
4.5V or more the ICM7555/6 will drive at least 2 standard
TTL loads.
ASTABLE OPERATION
The circuit can be connected to trigger itself and free run as
a multivibrator, see Figure 2A. The output swings from rail to
rail, and is a true 50% duty cycle square wave. (Trip points
and output swings are symmetrical). Less than a 1%
frequency variation is observed, over a voltage range of +5V
to +15V.
f = ₁----_.-₄---¹--_R-----_C---
The timer can also be connected as shown in Figure 2B. In this
circuit, the frequency is:
f = 1.44 ⁄ (RA + 2RB)C
The duty cycle is controlled by the values of R_A and R_B, by the
equation:
D = (RA + RB) ⁄ (RA + 2RB)
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot, see
Figure 3. Initially the external capacitor (C) is held discharged
by a transistor inside the timer. Upon application of a negative
TRIGGER pulse to pin 2, the internal flip-flop is set which
releases the short circuit across the external capacitor and
drives the OUTPUT high. The voltage across the capacitor now
increases exponentially with a
voltage across the capacitor
time constant t =
equals ²/₃ V+,
R_AC. When the
the comparator
resets the flip-flop, which in turn discharges the capacitor rap-
idly and also drives the OUTPUT to its low state. TRIGGER
must return to a high state before the OUTPUT can return to a
low state.
t_OUTPUT = -ln (1/3) R_AC = 1.1R_AC
V_DD
R_A
1
8
TRIGGER
OUTPUT
RESET
DISCHARGE
2
7
ICM7555
THRESHOLD
3
6
CONTROL
4
5 VOLTAGE
V_DD ≤18V
OPTIONAL
CAPACITOR
C
FIGURE 3. MONOSTABLE OPERATION
CONTROL VOLTAGE
The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal
comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or even
inhibition of oscillation, depending on the applied voltage. In
the monostable mode, delay times can be changed by
varying the applied voltage to the CONTROL VOLTAGE pin.
RESET
The RESET terminal is designed to have essentially the
same trip voltage as the standard bipolar 555/6, i.e., 0.6V to
0.7V. At all supply voltages it represents an extremely high
input impedance. The mode of operation of the RESET
function is, however, much improved over the standard
bipolar 555/6 in that it controls only the internal flip-flop,
which in turn controls simultaneously the state of the
OUTPUT and DISCHARGE pins. This avoids the multiple
threshold problems sometimes encountered with slow falling
edges in the bipolar devices.
5