HI5760 Datasheet, PDF (5/18 Pages) Intersil Corporation – 10-Bit, 125/60MSPS, High Speed D/A Converter

HI5760
Electrical Specifications
PARAMETER
AV_DD = DV_DD = +5V, V_REF = Internal 1.2V, IOUTFS = 20mA, T_A = 25^oC for All Typical Values (Continued)
HI5760
T_A = -40^oC TO 85^oC
TEST CONDITIONS
MIN TYP MAX UNITS
DIGITAL INPUTS D9-D0, CLK
Input Logic High Voltage with
5V Supply, V_IH
Input Logic High Voltage with
3V Supply, V_IH
Input Logic Low Voltage with
5V Supply, V_IL
Input Logic Low Voltage with
3V Supply, V_IL
Input Logic Current, I_IH
Input Logic Current, I_IL
Digital Input Capacitance, C_IN
TIMING CHARACTERISTICS
(Note 3)
(Note 3)
(Note 3)
(Note 3)
3.5
5
-
V
2.1
3
-
V
-
0
1.3
V
-
0
0.9
V
-10
-
+10
µA
-10
-
+10
µA
-
5
-
pF
Data Setup Time, t_SU
See Figure 41 (Note 3)
Data Hold Time, t_HLD
See Figure 41 (Note 3)
Propagation Delay Time, t_PD
See Figure 41
CLK Pulse Width, t_PW1, t_PW2
See Figure 41 (Note 3)
POWER SUPPLY CHARACTERISTICS
3
-
-
ns
3
-
-
ns
-
1
-
ns
4
-
-
ns
AV_DD Power Supply
DV_DD Power Supply
Analog Supply Current (I_AVDD)
(Note 8)
(Note 8)
(5V or 3V, IOUTFS = 20mA)
(5V or 3V, IOUTFS = 2mA)
2.7
5.0
5.5
V
2.7
5.0
5.5
V
-
23
30
mA
-
4
-
mA
Digital Supply Current (I_DVDD)
(5V, IOUTFS = Don’t Care) (Note 5)
(3V, IOUTFS = Don’t Care) (Note 5)
-
3
5
mA
-
1.5
-
mA
Supply Current (I_AVDD) Sleep Mode
Power Dissipation
(5V or 3V, IOUTFS = Don’t Care)
(5V, IOUTFS = 20mA) (Note 6)
-
1.6
3
mA
-
165
-
mW
(5V, IOUTFS = 2mA) (Note 6)
-
70
-
mW
(5V, IOUTFS = 20mA) (Note 9)
-
150
-
mW
(3.3V, IOUTFS = 20mA) (Note 9)
-
75
-
mW
(3V, IOUTFS = 20mA) (Note 6)
-
85
-
mW
(3V, IOUTFS = 20mA) (Note 9)
-
67
-
mW
(3V, IOUTFS = 2mA) (Note 6)
-
27
-
mW
Power Supply Rejection
Single Supply (Note 7)
-0.2
-
+0.2 % FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R_SET (typically 625µA). Ideally the
ratio should be 31.969.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential coupled transformer.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. See ‘Definition of Specifications’.
8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV_DD and
AV_DD do not have to be equal.
9. Measured with the clock at 60MSPS and the output frequency at 10MHz.
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