HI3338_04 Datasheet, PDF (5/9 Pages) Intersil Corporation – 8-Bit, CMOS R2R D/A Converter

HI3338
Pin Descriptions
PIN NAME
DESCRIPTION
1
D7 Most Significant Bit
2
D6
Input
3
D5
Data
4
D4
Bits
5
D3
(High = True)
6
D2
7
D1
8
V_SS Digital Ground
9
D0 Least Significant Bit. Input Data Bit
10
V_EE Analog Ground
11
V_REF- Reference Voltage Negative Input
12
V_OUT Analog Output
13 V_REF+ Reference Voltage Positive Input
14 COMP Data Complement Control input. Active High
15
LE Latch Enable Input. Active Low
16
V_DD Digital Power Supply, +5V
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 2⁰) through D7 (weighted 2⁷),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V_DD and V_SS, are shifted to operate between V_DD
and V_EE. V_EE optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V_DD
and V_EE supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t_D2
gives the delay from the input changing to the output
changing (10%), while t_SU2 and t_H give the set up and hold
times (referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given t_SU1 set up time to the LE falling edge,
and the t_H hold time from the LE rising edge. The delay to
the output changing, t_D1, is now referred to the LE falling
edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t_W pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus
the bottom “2R” resistor are returned to V_REF- this is the
(-) full-scale reference. The “P” channel (pull up) transistor
of each driver is returned to V_REF+, the (+) full-scale
reference.
In unipolar operation, V_REF- would typically be returned to
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
that flows from V_REF+ to V_REF- (see V_REF+ input current in
specifications), so V_REF- should have a low impedance path
to ground.
In bipolar operation, V_REF- would be returned to a negative
voltage (the maximum voltage rating to V_DD must be
observed). V_EE, which supplies the gate potential for the
output drivers, must be returned to a point at least as
negative as V_REF-. Note that the maximum clocking speed
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to V_REF-
with an input code of 00_HEX (zero scale output), and an
output equal to 255/256 of V_REF+ (referred to V_REF-) with
an input code of FFHEX (full scale output). The difference
between the ideal and actual values of these two parameters
are the OFFSET and GAIN errors, respectively; see
Figure 3.
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