EL5525 Datasheet, PDF (5/10 Pages) Intersil Corporation – 18-Channel TFT-LCD Reference Voltage Generator

EL5525
General Description
The EL5525 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5525,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5525. As all of the output
buffers are identical, it is also possible to use the EL5525 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
Digital Interface
The EL5525 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5525 can support
the clock rate up to 5MHz.
Serial Interface
The EL5525 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB
(bit 15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
To facilitate the system designs that use multiple EL5525
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
To control the multiple EL5525 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
Serial Timing Diagram
ENA
together, connect the SDO pin to the SDI pin on the next
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to Table 1).
• Bit 15 is always set to a zero
• Bits 14 through 10 select the channel to be written to, these
are binary coded with channel A = 0, and channel R = 17
• The 10-bit data is on bits 9 through 0. Some examples of
data words are shown in Table 3.
TABLE 1. CONTROL BITS LOGIC TABLE
BIT
NAME
DESCRIPTION
B15
Test
Always 0
B14
A4
Channel Address
B13
A3
Channel Address
B12
A2
Channel Address
B11
A1
Channel Address
B10
A0
Channel Address
B9
D9
Data
B8
D8
Data
B7
D7
Data
B6
D6
Data
B5
D5
Data
B4
D4
Data
B3
D3
Data
B2
D2
Data
B1
D1
Data
B0
D0
Data
t_HE
t_SE
t_r
T
t_{f tHE}
t_SE
SCLK
t_SD
t_HD
t_w
SDI
B15
B14
B13
B12-B2
B1
B0
t
MSB
LOAD MSB FIRST, LSB LAST
LSB
5
FN7393.2
September 21, 2010