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CA3310 Datasheet, PDF (5/15 Pages) Intersil Corporation – CMOS, 10-Bit, A/D Converters with Internal Track and Hold
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CA3310, CA3310A
Electrical Specifications TA = 25oC, VDD = VAA+ = 5V, VREF+ = 4.608V, VSS = VAA- = VREF- = GND, CLK = External 1MHz,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
DIGITAL OUTPUTS D0 - D9, DRDY
High-Level Output Voltage
ISOURCE = -4mA
4.6
Low-Level Output Voltage
ISINK = 6mA
-
Three-State Leakage
Except DRDY
-
Output Capacitance
Except DRDY (Note 2)
-
CLK OUTPUT
High-Level Output Voltage
ISOURCE = 100µA (Note 2)
4
Low-Level Output Voltage
ISlNK = 100µA (Note 2)
-
TIMING
Clock Frequency
Internal, CLK and REXT Open
200
Internal, CLK Shorted to REXT
600
External, Applied to CLK (Note 2) (Max)
-
(Min)
100
Clock Pulse Width, tLOW, tHIGH
External, Applied to CLK:
100
See Figure 1 (Note 2)
Conversion Time
Internal, CLK Shorted to REXT
13
Aperture Delay, tD APR
See Figure 1
-
Clock to Data Ready Delay, tD1 DRDY See Figure 1
-
Clock to Data Ready Delay, tD2 DRDY See Figure 1
-
Clock to Data Delay, tD Data
See Figure 1
-
Start Removal Time, tR STRT
See Figures 3 and 4 (Note 1)
-
Start Setup Time, tSU STRT
See Figure 4
-
Start Pulse Width, tW STRT
See Figures 3 and 4
-
Start to Data Ready Delay, tD3 DRDY
See Figures 3 and 4
-
Clock Delay from Start, tD CLK
See Figure 3
-
Ready Reset Removal Time, tR DRST
See Figure 50 (Note 1)
-
Ready Reset Pulse Width, tW DRST
See Figure 5
-
Ready Reset to Data Ready Delay,
See Figure 5
-
tD4 DRDY
Output Enable Delay, tEN
See Figure 2
-
Output Disable Delay, tDIS
See Figure 2
-
SUPPLIES
Supply Operating Range, VDD or VAA
(Note 2)
3
Supply Current, IDD + IAA
See Figures 14, 15
-
Supply Standby Current
Clock Stopped During Cycle 1
-
Analog Supply Rejection
At 120Hz, See Figure 13
-
Reference Input Current
See Figure 10
-
TEMPERATURE DEPENDENCY
Offset Drift
At 0 to 1 Code Transition
-
Gain Drift
At 1022 to 1023 Code Transition
-
Internal Clock Speed
See Figure 7
-
NOTES:
1. A (-) removal time means the signal can be removed after the reference signal.
2. Parameter not tested, but guaranteed by design or characterization.
TYP
-
-
-
-
-
-
300
800
4
10
-
-
100
150
250
200
-120
160
10
170
200
- 80
10
35
40
50
-
3
3.5
25
160
-4
-6
-0.5
MAX
-
0.4
±1
20
-
1
400
1000
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
8
-
-
-
-
-
-
UNITS
V
V
µA
pF
V
V
kHz
kHz
MHz
kHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
mA
mA
mV/ V
µA
µV/ oC
µV/ oC
% / oC
6-10
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