ISL94203_15 Datasheet, PDF (47/63 Pages) Intersil Corporation – 3-to-8 Cell Li-ion Battery Pack Monitor

ISL94203
WATCHDOG TIMER RESET
S
S
T
A
R
T
SLAVE
BYTE
REGISTER
ADDRESS
T
A
R
T
SLAVE
BYTE
NS
AT
CO
KP
SDA BUS _{0 1 0 1 0 0 0 0}
01010001
A
A
C
C
K
K
A
A
C
K
DATA
C
K
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 40. RANDOM READ SEQUENCE
WATCHDOG TIMER RESET
NS
SLAVE
AT
BYTE
CO
KP
1
A
C
K
DATA 1
A
C
K
DATA 2
A
A
C
K
DATA (n-1)
C
K
DATA (n)
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 41. SEQUENTIAL READ SEQUENCE
Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read operations:
Current Address Reads, Random Reads and Sequential Reads.
CURRENT ADDRESS READ
Internally the device contains an address counter that maintains
the address of the last word read incremented by one. Therefore,
if the last read was to address n, the next read operation would
access data from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write operation
for initialization. See Figure 42.
Upon receipt of the Slave Address Byte with the R/W bit set to
one, the device issues an acknowledge and then transmits the
eight bits of the Data Byte. The master terminates the read
operation when it does not respond with an acknowledge during
the ninth clock and then issues a stop condition.
the R/W bit set to one, the master must first perform a “dummy”
write operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then issues the
Word Address Bytes. After acknowledging receipts of the Word
Address Bytes, the master immediately issues another start
condition and the Slave Address Byte with the R/W bit set to one.
This is followed by an acknowledge from the device and then by
the eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a stop
condition (see Figure 40).
SEQUENTIAL READ
Sequential reads can be initiated as either a current address
read or random address read. The first Data Byte is transmitted
as with the other modes; however, the master now responds with
an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
It should be noted that the ninth clock cycle of the read operation
is not a “don’t care.” To terminate a read operation, the master
must either issue a stop condition during the ninth cycle or hold
SDA HIGH during the ninth clock cycle and then issue a stop
condition.
RANDOM READ
Random read operation allows the master to access any memory
location in the array. Prior to issuing the Slave Address Byte with
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter for
read operations increments through all page and column
addresses, allowing the entire memory contents to be serially
read during one operation. At the end of the address space the
counter “rolls over” to address 0000H and the device continues
to output data for each acknowledge received. See Figure 41 for
the acknowledge and data transfer sequence.
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FN7626.4
August 17, 2015