ISL28023_15 Datasheet, PDF (44/55 Pages) Intersil Corporation – Precision Digital Power Monitor with Margining

ISL28023
SMBus/I²C Serial Interface
The ISL28023 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL28023 operates as a slave device in all
applications.
The ISL28023 uses two bytes data transfer, all reads and writes
are required to use two data bytes. All communication over the
I²C interface is conducted by sending the MSByte of each byte of
data first, followed by the LSByte.
Protocol Conventions
For normal operation, data states on the SDA line can change
only during SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating START and STOP conditions (see
Figure 104). On power-up, the SDA pin is in the input mode.
All I²C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition is met (see Figure 104). A START condition is ignored
during the power-up sequence.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW-to-HIGH transition of SDA while SCL is
HIGH (see Figure 104). A STOP condition at the end of a read
operation or at the end of a write operation places the device in its
standby mode.
SMBus, PMBus Support
The ISL28023 supports SMBus and PMBus protocol, which is a
subset of the global I²C protocol. SMBCLK and SMBDAT have the
same pin functionality as the SCL and SDA pins, respectively. The
SMBus operates at 100kHz. The PMBus protocol standardizes
the functionality of each register by address.
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
FIGURE 104. VALID DATA CHANGES, START AND STOP CONDITIONS
STOP
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH
START
FIGURE 105. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM THE
MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL28023
S
WRITE
T
A ^{IDENTIFICATION}
R
BYTE
ADDRESS
BYTE
T
DATA
BYTE
S
DATA
T
BYTE
O
P
1nnnnnn0 0000
A
A
A
A
C
C
C
C
K
K
K
K
FIGURE 106. BYTE WRITE SEQUENCE (SLAVE ADDRESS INDICATED BY nnnnnn)
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FN8389.4
June 17, 2015