X95840_06 Datasheet, PDF (4/13 Pages) Intersil Corporation – Quad Digital Controlled Potentiometers

X95840
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
I_CC1
I_CC2
I_SB
I_LkgDig
PARAMETER
TEST CONDITIONS
V_CC Supply Current
(Volatile write/read)
f_SCL = 400kHz; SDA = Open; (for I²C,
Active, Read and Volatile Write States only)
V_CC Supply Current
(nonvolatile write)
f_SCL = 400kHz; SDA = Open; (for I²C,
Active, Nonvolatile Write State only)
V_CC Current (standby)
V_CC = +5.5V, I²C Interface in Standby State
V_CC = +3.6V, I²C Interface in Standby State
Leakage Current, at
Voltage at pin from GND to V_CC
Pins A0, A1, A2, SDA, SCL,
and WP Pins
TYP
MIN (Note 1) MAX
1
UNITS
mA
3
mA
5
µA
2
µA
-10
10
µA
t_DCP
DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to wiper
(Note 15)
change
1
µs
Vpor
Power-on Recall Voltage
Minimum V_CC at which memory recall occurs
1.8
VccRamp V_CC Ramp Rate
0.2
t_D (Note 15) Power-up Delay
V_CC above
completed,
Vpor, to
and I²C
DCP Initial Value Register
Interface in standby state
recall
2.6
V
V/ms
3
ms
EEPROM SPECS
EEPROM Endurance
150,000
Cycles
EEPROM Retention
Temperature ≤ 75°C
50
Years
SERIAL INTERFACE SPECS
V_IL
WP, A2, A1, A0, SDA, and
SCL Input Buffer LOW
Voltage
-0.3
0.3*V_CC
V
V_IH
WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
0.7*V_CC
V_CC+0.3
V
Hysteresis SDA and SCL Input Buffer
(Note 15) Hysteresis
V_OL (Note 15) SDA outPut Buffer LOW
Voltage, Sinking 4mA
0.05*
V_CC
0
V
0.4
V
Cpin
WP, A2, A1, A0, SDA, and
(Note 15) SCL Pin Capacitance
10
pF
f_SCL
SCL frEquency
t_IN (Note 15) Pulse Width Suppression Any pulse narrower than the max spec is suppressed.
Time at SDA and SCL Inputs
400
kHz
50
ns
t_AA (Note 15) SCL Falling Edge to SDA
Output Data Valid
t_BUF
(Note 15)
Time the Bus Must be Free
Before the Start of a New
Transmission
SCL falling edge crossing 30% of V_CC, until SDA exits
the 30% to 70% of V_CC window.
SDA crossing 70% of V_CC during a STOP condition, to
SDA crossing 70% of V_CC during the following START
condition.
1300
900
ns
ns
t_LOW
Clock LOW Time
Measured at the 30% of V_CC crossing.
1300
ns
t_HIGH
Clock HIGH Time
Measured at the 70% of V_CC crossing.
600
ns
t_SU:STA START Condition Setup
SCL rising edge to SDA falling edge. Both crossing
600
ns
Time
70% of V_CC.
t_HD:STA START Condition Hold Time From SDA falling edge crossing 30% of V_CC to SCL
600
ns
falling edge crossing 70% of V_CC.
4
FN8213.2
July 5, 2006