X95820_06 Datasheet, PDF (4/12 Pages) Intersil Corporation – Dual Digital Controlled Potentiometers

X95820
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
I_CC1
I_CC2
I_SB
I_LkgDig
PARAMETER
TEST CONDITIONS
V_CC Supply Current
(Volatile write/read)
f_SCL = 400kHz;SDA = Open; (for I²C,
Active, Read and Volatile Write States only)
V_CC Supply Current
(nonvolatile write)
f_SCL = 400kHz; SDA = Open; (for I²C,
Active, Nonvolatile Write State only)
V_CC Current (standby)
V_CC = +5.5V, I²C Interface in Standby State
V_CC = +3.6V, I²C Interface in Standby State
Leakage Current, at Pins A0, Voltage at pin from GND to V_CC
A1, A2, SDA, SCL, and WP
Pins
TYP
MIN (Note 1) MAX
1
3
5
2
-10
10
t_DCP
DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to
1
(Note 15)
wiper change
Vpor
Power-on Recall Voltage
Minimum V_CC at which memory recall occurs
1.8
2.6
VccRamp V_CC Ramp Rate
0.2
t_D (Note 15) Power-up Delay
V_CC above
completed,
Vpor, to DCP Initial Value Register recall
and I²C Interface in standby state
3
EEPROM SPECS
EEPROM Endurance
150,000
EEPROM Retention
Temperature ≤ 75°C
50
SERIAL INTERFACE SPECS
V_IL
WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage
-0.3
0.3*Vcc
V_IH
WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
0.7*Vcc
Vcc+0.3
Hysterisis SDA and SCL input buffer
(Note 15) hysterisis
0.05*
Vcc
V_OL
SDA Output Buffer LOW
(Note 15) Voltage, Sinking 4mA
0
0.4
Cpin
WP, A2, A1, A0, SDA, and
10
(Note 15) SCL Pin Capacitance
f_SCL
SCL Frequency
400
t_IN
Pulse Width Suppression Any pulse narrower than the max spec is
50
(Note 15) Time at SDA and SCL Inputs suppressed.
t_AA
SCL Falling Edge to SDA SCL falling edge crossing 30% of V_CC, until SDA
900
(Note 15) Output Data Valid
exits the 30% to 70% of V_CC window.
t_BUF
(Note 15)
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of V_CC during a STOP condition,
to SDA crossing 70% of V_CC during the following
START condition.
1300
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
Clock LOW Time
Measured at the 30% of V_CC crossing.
Clock HIGH Time
Measured at the 70% of V_CC crossing.
START Condition Setup
Time
SCL rising edge to SDA falling edge. Both crossing
70% of V_CC.
START Condition Hold Time From SDA falling edge crossing 30% of V_CC to SCL
falling edge crossing 70% of V_CC.
1300
600
600
600
UNITS
mA
mA
µA
µA
µA
µs
V
V/ms
ms
Cycles
Years
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
4
FN8212.2
July 18, 2006