X24C45 Datasheet, PDF (4/12 Pages) Xicor Inc. – Serial AUTOSTORE™ NOVRAM

X24C45
WRITE
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must remain
HIGH during the entire operation. CE must go LOW
before the next rising edge of SK. If CE is brought LOW
prematurely (after the instruction but before 16 bits of
data are transferred), the instruction register will be reset
and the data that was shifted-in will be written to RAM.
If CE is kept HIGH for more than 24 SK clock cycles
(8-bit instruction plus 16-bit data), the data already
shifted-in will be overwritten.
READ
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions,
I₀ of the instruction word is a "don’t care". This pro-
vides two advantages. In a design that ties both DI
and DO together, the absence of an eighth bit in the
instruction allows the host time to convert an I/O line
from an output to an input. Secondly, it allows for valid
data output during the ninth SK clock cycle.
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling
edge of the eighth SK clock; whereas, all succeeding
bits are clocked by the rising edge of SK (refer to Read
Cycle Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby
power mode, thereby minimizing power consumption.
AUTOSTORE Feature
The AUTOSTORE instruction (ENAS) sets the
"AUTOSTORE enable" latch, allowing the X24C45 to
automatically perform a store operation when V_CC falls
below the AUTOSTORE threshold (V_ASTH).
Notes: X = Don't Care
A = Address
WRITE PROTECTION
The X24C45 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
Upon power-up the "write enable" and "AUTOSTORE
enable" latches are in the reset state, disabling any
store operation.
Unknown Data Store
The "previous recall" latch must be set after power-up.
It may be set only by performing a software or hard-
ware recall operation, which assures that data in all
RAM locations is valid.
SYSTEM CONSIDERATIONS
Power-Up Recall
The X24C45 performs a power-up recall that transfers
the EEPROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the "previous recall" latch. During this power-
up recall operation, all commands are ignored. There-
fore, the host should delay any operations with the
X24C45 a minimum of t_PUR after V_CC is stable.
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FN8104.0
June 1, 2005