ISL6611A_14 Datasheet, PDF (4/14 Pages) Intersil Corporation – Phase Doubler with Integrated Drivers and Phase Shedding Function

ISL6611A
Functional Pin Descriptions
PACKAGE
PIN #
1
2
3
4
5
6
7
PIN
SYMBOL
FUNCTION
GND
Bias and reference ground. All signals are referenced to this node. It is also the return of the sample and hold of the
r_DS(ON) current sensing circuits. Place a high quality low ESR ceramic capacitor from this pin to VCC.
LGATEA Lower gate drive output of Channel A. Connect to gate of the low-side power N-Channel MOSFET.
PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from
this pin to PGND.
IGAIN A resistor from this pin to GND sets the current balance gain. See “Current Balance and Maximum Frequency” on
page 11 for more details.
PGND Power ground return of both low gate drivers. It is also the return of the phase node clamp circuits.
LGATEB Lower gate drive output of Channel B. Connect to gate of the low-side power N-Channel MOSFET.
EN_PH Driver Enable Input. A signal high input enables the driver at the PWM rising edge, a signal low input pulls PWM pin to
VCC at the PWM falling edge and then enters tri-state.
8
PHASEB Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel B. This pin
provides a return path for the upper gate drive.
9
UGATEB Upper gate drive output of Channel B. Connect to gate of high-side power N-Channel MOSFET.
10
BOOTB Floating bootstrap supply pin for the upper gate drive of Channel B. Connect the bootstrap capacitor between this pin
and the PHASEB pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See“Bootstrap
Considerations” on page 9 for guidance in choosing the capacitor value.
11
BOOTA Floating bootstrap supply pin for the upper gate drive of Channel A. Connect the bootstrap capacitor between this pin
and the PHASEA pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap
Considerations” on page 9 for guidance in choosing the capacitor value.
12
UGATEA Upper gate drive output of Channel A. Connect to gate of high-side power N-Channel MOSFET.
13
PHASEA Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel A. This pin
provides a return path for the upper gate drive.
14
VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
15
PWM The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels are effectively
modulated. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 9 for
further details. Connect this pin to the PWM output of the controller. The pin is pulled to VCC when EN_PH is low and
the PWM input starts transitioning low.
16
SYNC A signal high synchronizes both channels with no phase shifted. A signal low interleaves both channels with 180°
out-of-phase.
17
PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
4
FN6881.1
August 28, 2012