ISL43485 Datasheet, PDF (4/11 Pages) Intersil Corporation – 3.3V, Low Power, 30Mbps, RS-485/RS-422

ISL43485
Electrical Specifications Test Conditions: V_CC = 3V to 3.6V; Unless Otherwise Specified. Typicals are at V_CC = 3.3V, T_A = 25°C,
Note 2 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C) MIN
TYP MAX UNITS
Three-State (high impedance)
Receiver Output Current
I_OZR 0.4V ≤ V_O ≤ 2.4V
Full
-1
-
1
µA
Receiver Input Resistance
No-Load Supply Current (Note 3)
R_IN
-7V ≤ V_CM ≤ 12V
I_CC
DI = 0V or V_CC
Full 12
19
-
kΩ
DE = V_CC, Full
-
0.75 1.2 mA
RE = 0V
or V_CC
DE = 0V, Full
-
0.65
1
mA
RE = 0V
Shutdown Supply Current
I_SHDN
Driver Short-Circuit Current,
V_O = High or Low
I_OSD1
Receiver Short-Circuit Current
I_OSR
DRIVER SWITCHING CHARACTERISTICS
DE = 0V, RE = V_CC, DI = 0V or V_CC
DE = V_CC, -7V ≤ V_Y or V_Z ≤ 12V (Note 4)
0V ≤ V_O ≤ V_CC
Full
-
Full
-
Full
8
15
100 nA
-
250 mA
-
60
mA
Maximum Data Rate
f_MAX (Figure 2A)
Driver Differential Output Delay
t_DD
R_DIFF = 60Ω, C_L = 15pF (Figure 2A)
Driver Differential Rise or Fall Time t_R, t_F R_DIFF = 60Ω, C_L = 15pF (Figure 2A)
Driver Input to Output Delay
t_PLH, t_PHL R_L = 27Ω, C_L = 15pF (Figure 2C)
Driver Output Skew
t_SKEW R_L = 27Ω, C_L = 15pF (Figure 2C)
Driver Enable to Output High
t_ZH
R_L = 110Ω, C_L = 50pF, SW = GND (Figure 3),
(Note 5)
Full 30
50
-
Mbps
Full
3
10
25
ns
Full
3
6
12
ns
Full
6
10
22
ns
Full
-
1
5
ns
Full
-
45
90
ns
Driver Enable to Output Low
t_ZL
R_L = 110Ω, C_L = 50pF, SW = V_CC (Figure 3),
(Note 5)
Full
-
45
90
ns
Driver Disable from Output High
Driver Disable from Output Low
Driver Enable from Shutdown to
Output High
t_HZ
R_L = 110Ω, C_L = 50pF, SW = GND (Figure 3)
t_LZ
R_L = 110Ω, C_L = 50pF, SW = V_CC (Figure 3)
t_ZH(SHDN) R_L = 110Ω, C_L = 50pF, SW = GND (Figure 3),
(Notes 7, 8)
Full
-
Full
-
Full
-
60
90
ns
70
100
ns
115 150 ns
Driver Enable from Shutdown to
Output Low
t_ZL(SHDN) R_L = 110Ω, C_L = 50pF, SW = V_CC (Figure 3),
(Notes 7, 8)
Full
-
115 150 ns
RECEIVER SWITCHING CHARACTERISTICS
Maximum Data Rate
f_MAX
V_ID ≥ 1.5V with t_r/t_f = 10ns, RO t_H & t_L ≥ 60% t_UI Full
27
35
(Figure 4)
-
Mbps
Receiver Input to Output Delay
Receiver Skew | t_PLH - t_PHL |
Receiver Enable to Output High
t_PLH, t_PHL (Figure 4)
t_SKD (Figure 4)
t_ZH
R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 5),
(Note 6)
Full 25
45
80
ns
Full
-
2
12
ns
Full
-
11
25
ns
Receiver Enable to Output Low
t_ZL
R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 5),
(Note 6)
Full
-
11
25
ns
Receiver Disable from Output High
t_HZ
R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 5)
Receiver Disable from Output Low
t_LZ
R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 5)
Full
-
Full
-
7
20
ns
7
20
ns
4