HSP48901 Datasheet, PDF (4/9 Pages) Intersil Corporation – 3 x 3 Image Filter

HSP48901
Functional Description
The HSP48901 can perform convolution of a 3 x 3 filter kernel
with 8-bit image data. It accepts the image data in a raster
scan, non-interlaced format, convolves it with the filter kernel
and outputs the filtered image. The input and filter kernel data
are both 8-bits, while the output data is 20 bits to prevent
overflow during the convolution operation. Image data is input
via the DIN1, DIN2, and DIN3 busses. This data would
normally be provided by programmable data buffer such as
the HSP9501 as illustrated in the Operations Section of this
specification. The data is then convolved with the 3 x 3 array
of filter coefficients. The resultant output data is then stored in
the Output Register. The HSP48901 may also be used in a
one-dimensional mode. In this configuration, it functions as a
1-D 9-tap FIR filter. Data would be input via the DIN1(0-7) bus
for operation in this mode.
Initialization of the convolver is done using the CIN0-7 bus to
load configuration data and the filter kernel(s). The address
lines A0-2 are used to address the Internal Registers for
initialization. The configuration data is loaded using the
A0-2, CIN0-7 and LD controls as address, data and write
enable, respectively. This interface is compatible with
standard microprocessors without the use of any additional
glue logic.
Filtered image data is output from the convolver over the
DOUT0-19 bus. This output bus is 20 bits wide to provide
room for growth during the convolution operation.
8-Bit Multiplier Array
The multiplier array consists of nine 8 x 8 multipliers. Each
multiplier forms the product of a filter coefficient with a
corresponding pixel in the input image. Input and coefficient
data may be in either two's complement or unsigned integer
format. The nine coefficients form a 3 x 3 filter kernel which
is multiplied by the input pixel data and summed to form a
sum of products for implementation of the convolution
operation as shown below:
FILTER KERNEL
A
B
C
D
E
F
G
H
I
INPUT DATA
P1
P2
P3
P4
P5
P6
P7
P8
P9
OUTPUT = (A x P1) + (B x P2) + (C x P3)
+ (D x P4) + (E x P5) + (F x P6)
+ (G x P7) + (H x P8) + (I x P9)
Control Logic
The control logic (Figure 1) contains the Initialization
Register and the Coefficient Registers. The control logic is
updated by placing data on the CIN0-7 bus and using the
A0-2 and LD control lines to write to the addressed register
(see Address Decoder). All of the Control Logic Registers
are unaffected by FRAME.
3
A0 - 2
LD
ADDRESS
CODE
ENCRO
ENCR1
CAS
CR1
CRO
CIN0 - 7
CR0
INITIALIZATION REGISTER
(INT)
INITIALIZATION
DATA
CAS
COEFFICIENT
REGISTER 0
I0 E H0 E G0 E F0 E E0 E D0 E C0 E B0 E A0 E
I
H
G
F
E
D
C
B
A
CR1
ENCR1
ENCR0
SQ
CQ
I1 E
H1 E
G1 E
F1 E E1 E D1 E
COEFFICIENT
REGISTER 1
C1 E
B1 E A1 E
FIGURE 1. CONTROL LOGIC BLOCK DIAGRAM
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