HSP43216_08 Datasheet, PDF (4/20 Pages) Intersil Corporation – Halfband Filter

HSP43216
INPUT DATA FLOW
CONTROLLER
AIN0-15 R
R
E
E
G
G
M
U
BIN0-15
RR
EE
X
GG
CLK
MODE0-1
SYNC
INT/EXT
RND0-2
FMT
USB/LSB
f_S/4 QUADRATURE 67-TAP HALFBAND f_S/4 QUADRATURE
DOWN CONVERT
FILTER
UP CONVERT
PROCESSOR
PROCESSOR
PROCESSOR
†
†
R
R
E
E
G
G
MUX
1,-1,1,..
1
1 _-1,1,-1,.
PIPELINE
† DELAY 2 - 35
†
EVEN TAP
R
FILTER
E
G
SYNC
USB/LSB
MUX
f_S/4
L.O.
...,2,-2,2
..,-2,2,-2
12
12
MUX
†
†
R
R
E
E
G
G
PIPELINE
† DELAY 19
ODD TAP
FILTER
MUX
†
R
E
G
OUTPUT DATA FLOW
CONTROLLER
R
E
G
M _RFRR
U NMEE
X ^{D TGG}
AOUT0-15
OEA
+
RFRR
NME E
D T GG
BOUT0-15
OEB
† Indicates elements which operate at CLK/2 when the INT/EXT control input is high.
FIGURE 1. HALFBAND BLOCK DIAGRAM
Functional Description
The operation of the HSP43216 centers around a fixed
coefficient, 67-Tap, Halfband Filter Processor as shown in
Figure 1. The Halfband Filter Processor operates stand
alone to provide two fundamental modes of operation:
interpolate or decimate by two filtering of a real signal. In two
other modes, the Quadrature Up/Down Convert circuitry
operates together with the Filter Processor block to provide
f_S/4 Down Conversion with decimate by 2 filtering or
Quadrature to Real Conversion.
In Down Convert and Decimate mode, a real input sample
stream is spectrally shifted by f_S/4. Each component of the
resulting complex signal is then halfband filtered and
decimated by 2 to produce real and imaginary output
samples at half of the input data rate.
In Quadrature to Real Conversion mode, the real and
imaginary components of a quadrature input are interpolated
by two and halfband filtered. The filtered result is then
spectrally shifted by f_S/4 and the real component of this
operation is output at twice the input sample rate.The
HSP43216 is configured for different operational modes by
setting the state of the mode control pins, MODE1-0 as
shown in Table 1.
TABLE 1. MODE SELECT TABLE
MODE1-0
MODE
00
Decimate by Two
01
Interpolate by Two
10
Down Convert and Decimate
11
Quadrature to Real Conversion
Input Data Flow Controller
The Input Data Flow Controller routes data samples from the
AIN0-15 and BIN0-15 inputs to the internal processing
elements of the Halfband. The data routing paths are based
on mode of operation and are more fully discussed in the
Operational Modes section.
f_S/4 Quadrature Down Convert Processor
The f_S/4 Quadrature Down Convert Processor operates as a
Quadrature LO which provides the negative f_S/4 spectral
shift required to center the upper sideband of a real input
signal at DC. This operation is equivalent to multiplying the
real sample stream, x(n), by the quadrature components of
the complex exponential e^-j(π/2)n as given below:
x(n)e^{–j(πn ⁄ 2)} = x(n) cos(πn ⁄ 2) + jx(n) sin(–πn ⁄ 2) (EQ. 1)
4
FN3365.10
October 6, 2008