HI5960_05 Datasheet, PDF (4/12 Pages) Intersil Corporation – 14-Bit, 125+MSPS, CommLinkTM High Speed D/A Converter

HI5960
Absolute Maximum Ratings
Digital Supply Voltage DV_DD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AV_DD to ACOM . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV_DD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV_DD + 0.3V
Analog Output Current (I_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
HI5960IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40^oC to 85^oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θ_JA(^oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150^oC
Maximum Storage Temperature Range . . . . . . . . . -65^oC to 150^oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300^oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ_JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AV_DD = DV_DD = +5V, V_REF = Internal 1.2V, IOUTFS = 20mA, T_A = 25^oC for All Typical Values
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE
Resolution
14
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-5
±2.5
+5
LSB
Differential Linearity Error, DNL
(Note 8)
-3
±1.5
+3
LSB
Offset Error, I_OS
Offset Drift Coefficient
(Note 8)
(Note 8)
-0.025
+0.025 % FSR
-
0.1
-
ppm
FSR/^oΧ
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10
±2
+10 % FSR
With Internal Reference (Notes 2, 8)
-10
±1
+10 % FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
±50
-
ppm
FSR/^οΧ
With Internal Reference (Note 8)
-
±100
-
ppm
FSR/^οΧ
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Note 3, 8)
2
-
20
mA
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f_CLK
Output Settling Time, (t_SETT)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
(Note 3)
±0.05% (±8 LSB) (Note 8)
R_L = 25Ω (Note 8)
Full Scale Step
130
-
-
MHz
-
35
-
ns
-
5
-
pV•s
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
Output Capacitance
-
10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/ √Hz
IOUTFS = 2mA
-
30
-
pA/ √Hz
AC CHARACTERISTICS
+5V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
f_CLK = 100MSPS, f_OUT = 20.2MHz, 30MHz Span (Notes 4, 8)
f_CLK = 100MSPS, f_OUT = 5.04MHz, 8MHz Span (Notes 4, 8)
f_CLK = 50MSPS, f_OUT = 5.02MHz, 8MHz Span (Notes 4, 8)
-
77
-
dBc
-
97
-
dBc
-
97
-
dBc
4