DG201A Datasheet, PDF (4/7 Pages) Intersil Corporation – Quad SPST, CMOS Analog Switches

DG201A, DG202
Test Circuits and Waveforms
LOGIC† _3V
INPUT
t_r < 20ns
t_f < 20ns
SWITCH
INPUT _VS
SWITCH
OUTPUT
LOGIC “0” = SWITCH ON
50%
90%
t_ON
90%
t_OFF
†Logic shown for DG201A, invert for DG202.
R_L
V_O = V_{S RL + rDS(ON)}
SWITCH
INPUT _S1
V_S = 2V
LOGIC ^IN1
INPUT
GND
15V
V+
D₁
R_L
1kΩ
SWITCH
OUTPUT
V_O
C_L
35pF
V-
-15V
(REPEAT TEST FOR
IN₂, IN₃ AND IN₄)
FIGURE 1. t_ON AND t_OFF SWITCHING TEST CIRCUIT AND MEASUREMENT POINTS
R_S
S_X
D_X
V_O
V_S
IN_X
C_L = 1nF
SWITCH
OUTPUT
IN_X
ON
OFF
NOTES:
6. ∆V_O = Measured voltage error due to charge injection.
7. The error in coulombs is Q = C_L x ∆V_O.
FIGURE 2. CHARGE INJECTION TEST CIRCUIT AND MEASUREMENT POINTS
∆V_O
ON
+15V
C
SIGNAL
GENERATOR
V+
V_S
V_S
ANALYZER
CHAN A
CHAN B
IN_X
V_IN
V_D
GND
V-
R_L
C
-15V
C = 0.001µF||0.1µF
Chip Capacitors
OIRR = 20 Log _V-^V_----DS--
FIGURE 3. OFF ISOLATION TEST CIRCUIT
4-4
+15V
C
SIGNAL
GENERATOR
V+
3 V_S1
V_D1
50Ω
V_S
ANALYZER
CHAN A
CHAN B
0V,
2.4V
R_L
IN₁
V_D2
GND
IN₂
0V, 2.4V
V_S2
NC
V-
C
-15V
C = 0.001µF||0.1µF
Chip Capacitors
CCRR = 20 Log _-^V_----^S_----¹_--
VD₂
FIGURE 4. CHANNEL TO CHANNEL CROSSTALK TEST
CIRCUIT