HFA3860B Datasheet, PDF (37/40 Pages) Intersil Corporation – Direct Sequence Spread Spectrum Baseband Processor

HFA3860B
Electrical Specifications V_CC = 3.0V to 3.3V ±10%, T_A = -40^oC to 85^oC (Note 10) (Continued)
MCLK = 44MHz
PARAMETER
SYMBOL
MIN
MAX
UNITS
TXD Modulation Extension
RX_PE Inactive Width
RX_CLK Period (11Mbps Mode)
RX_CLK Width Hi or Low (11Mbps Mode)
RX_CLK to RXD
MD_RDY to 1st RX_CLK
RXD to 1st RX_CLK
Setup RXD to RX_CLK
RX_CLK to RX_PE Inactive (1Mbps)
RX_CLK to RX_PE Inactive (2Mbps)
RX_CLK to RX_PE Inactive (5.5Mbps)
RX_CLK to RX_PE Inactive (11Mbps)
RX_PE inactive to MD_RDY Inactive
Last Chip of SFD in to MD_RDY Active
RX Delay
t_ME
t_RLP
t_RCP
t_RCD
t_RDD
t_RD1
t_RD1
t_RDS
t_REH
t_REH
t_REH
t_REH
t_RD2
t_RD3
2
70
77
31
25
940
940
31
0
0
0
0
5
2.77
2.77
-
µs (Notes 11, 15)
-
ns (Notes 11, 16)
-
ns
-
ns
60
ns
-
ns (Notes 11, 19)
-
ns
-
ns
925
ns (Notes 11, 17)
380
ns (Notes 11, 17)
140
ns (Notes 11, 17)
50
ns (Notes 11, 17)
30
ns (Note 18)
2.86
µs (Notes 11, 19)
2.86
µs (Notes 11, 20)
RESET Width Active
RX_PE to CCA Valid
RX_PE to RSSI Valid
ANTSEL Lead Time
t_RPW
50
t_CCA
-
t_CCA
-
820
-
ns (Notes 11, 21)
16
µs (Notes 11, 22)
16
µs (Notes 11, 22)
-
ns (Notes 11, 23)
SCLK Clock Period
t_SCP
90
-
ns
SCLK Width Hi or Low
t_SCW
20
-
ns
Setup to SCLK + Edge (SD, SDI, R/W, CS)
t_SCS
30
-
ns
Hold Time from SCLK + Edge (SD, SDI, R/W, CS)
t_SCH
0
-
ns
SD Out Delay from SCLK + Edge
t_SCD
-
30
ns
SD Out Enable/Disable from R/W or CS
t_SCED
-
15
ns (Note 11)
TEST 0-7, CCA, ANTSEL, TEST_CK from MCLK
t_D2
-
40
ns
NOTES:
10. AC tests performed with C_L = 40pF, I_OL = 2mA, and I_OH = -1mA. Input reference level all inputs 1.5V. Test V_IH = V_CC, V_IL = 0V; V_OH = V_OL = V_CC/2.
11. Not tested, but characterized at initial design and at major process/design or guaranteed by simulations.
12. Measured from V_IL to V_IH.
13. I_OUT/Q_OUT are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits.
14. TX_PE must be inactive before going active to generate a new packet.
15. I_OUT/Q_OUT are modulated after last chip of valid data to provide ramp down time for RF/IF circuits.
16. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition.
17. RX_PE active to inactive delay to prevent next RX_CLK.
18. Assumes RX_PE inactive after last RX_CLK.
19. MD_RDY programmed to go active after SFD detect. (Measured from I_IN, Q_IN).
20. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at I_IN, Q_IN to MD_RDY active.
21. Minimum time to insure Reset. RESET must be followed by an RX_PE pulse to insure proper operation. This pulse should not be used for first
receive or acquisition.
22. CCA and RSSI are measured once during the first 16µs interval following RX_PE going active. RX_PE must be pulsed to initiate a new
measurement. RSSI may be read via serial port or from Test Bus.
23. ANTSEL is switched in diversity mode before acquisition cycle to compensate for delays in IF circuits. The correlators will be 100X(820ns -
TdRFns)/990ns% full of new data at the beginning of bit sync accumulation. TdRFns is the settling time of the RF circuits after ANTSEL switches.
24. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within
40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns.
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