ZL2004 Datasheet, PDF (33/42 Pages) Intersil Corporation – Adaptive Digital DC-DC Controller with Current Sharing

ZL2004
Table 22. SMBus Address Values
R_SA
SMBus
Address
R_SA
10 kΩ
0x00
34.8 kΩ
11 kΩ
0x01
38.3 kΩ
12.1 kΩ
0x02
42.2 kΩ
13.3 kΩ
0x03
46.4 kΩ
14.7 kΩ
0x04
51.1 kΩ
16.2 kΩ
0x05
56.2 kΩ
17.8 kΩ
0x06
61.9 kΩ
19.6 kΩ
0x07
68.1 kΩ
21.5 kΩ
0x08
75 kΩ
23.7 kΩ
0x09
82.5 kΩ
26.1 kΩ
0x0A
90.9 kΩ
28.7 kΩ
0x0B
100 kΩ
31.6 kΩ
0x0C
SMBus
Address
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Using this method, the user can theoretically configure
up to 625 unique SMBus addresses, however the
SMBus is inherently limited to 128 devices so
attempting to configure an address higher than 128
(0x80) will cause the device address to repeat (i.e,
attempting to configure a device address of 129 (0x81)
would result in a device address of 1. Therefore, the
user should use index values 0-4 on the SA1 pin and
the full range of index values on the SA0 pin, which
will provide 125 device address combinations.
Table 23. SMBus Address Index Values
SA0 or
R_SA
SA1
Index
R_SA
SA0 or
SA1 Index
10 kΩ
0
34.8 kΩ
13
11 kΩ
1
38.3 kΩ
14
12.1 kΩ
2
42.2 kΩ
15
13.3 kΩ
3
46.4 kΩ
16
14.7 kΩ
4
51.1 kΩ
17
16.2 kΩ
5
56.2 kΩ
18
17.8 kΩ
6
61.9 kΩ
19
19.6 kΩ
7
68.1 kΩ
20
21.5 kΩ
8
75 kΩ
21
23.7 kΩ
9
82.5 kΩ
22
26.1 kΩ
10
90.9 kΩ
23
28.7 kΩ
11
100 kΩ
24
31.6 kΩ
12
6.11 Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Zilker Labs Digital-DC devices.
This dedicated bus provides the communication
channel between devices for features such as
sequencing, fault spreading, and current sharing. The
DDC pin on all Digital-DC devices in an application
should be connected together. A pull-up resistor is
required on the DDC bus in order to guarantee the rise
time as follows:
Rise time = R_PU * C_LOAD ≈ 1 µs,
where R_PU is the DDC bus pull-up resistance and
C_LOAD is the bus loading. The pull-up resistor may be
tied to VR or to an external 3.3V or 5V supply as long
as this voltage is present prior to or during device
power-up. As rules of thumb, each device connected to
the DDC bus presents approx 10 pF of capacitive
loading, and each inch of FR4 PCB trace introduces
approx 2 pF. The ideal design will use a central pull-up
resistor that is well-matched to the total load
capacitance. In power module applications, the user
should consider whether to place the pull-up resistor on
the module or on the PCB of the end application. The
minimum pull-up resistance should be limited to a
value that enables any device to assert the bus to a
voltage that will ensure a logic 0 (typically 0.8 V at the
device monitoring point) given the pull-up voltage (5
V if tied to VR) and the pull-down current capability of
the ZL2004 (nominally 4 mA).
6.12 Phase Spreading
When multiple point of load converters share a
common DC input supply, it is desirable to adjust the
clock phase offset of each device such that not all
devices start to switch simultaneously. Setting each
converter to start its switching cycle at a different point
in time can dramatically reduce input capacitance
requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively
spread out over a period of time, the peak current
drawn at any given moment is reduced and the power
losses proportional to the I_RMS2 are reduced
dramatically.
33
Data Sheet Revision 2/18/2009
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