X9409 Datasheet, PDF (3/20 Pages) Xicor Inc. – Quad Digitally Controlled Potentiometers

X9409
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9409.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A₀ - A₃)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9409. A maximum of 16 devices may occupy the
2-wire serial bus.
Potentiometer Pins
V_H0/R_H0 - V_H3/R_H3, V_L0/R_L0 - V_L3/R_L3
The V_H/R_H and V_L/R_L inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
PIN CONFIGURATION
V_W0/R_{W0 -} V_W3/R_W3
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
PIN NAMES
Symbol
SCL
SDA
A0-A3
V_H0/R_H0 - V_H3/R_H3,
V_L0/R_L0 - V_L3/R_L3
V_W0/R_W0 - V_W3/R_W3
WP
V_CC
V_SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pin
(terminal equivalent)
Potentiometer Pin
(wiper equivalent)
Hardware Write Protection
System Supply Voltage
System Ground (Digital)
No Connection
V_CC
V_L0/R_L0
V_H0/R_H0
V_W0/R_W0
A₂
WP
SDA
A₁
V_L1/R_L1
V_H1/R_H1
V_W1/R_W1
V _SS
SOIC
1
24
2
23
3
22
4
21
5
20
6
19
X9409
7
18
8
17
9
16
10
15
11
14
12
13
NC
V_L3/R_L3
V_H3/R_H3
V_W3/R_W3
A₀
NC
A₃
SCL
V_L2/R_L2
V_H2/R_H2
V_W2/R_W2
NC
SDA
A₁
V_L1/R_L1
V_H1/R_H1
V_W1/R_W1
V_SS
NC
V_W2/R_W2
V_H2/R_H2
V_L2/R_L2
SCL
A₃
TSSOP
1
24
2
23
3
22
4
21
5
20
6
19
X9409
7
18
8
17
9
16
10
15
11
14
12
13
WP
A₂
V_W0/R_W0
V_H0/R_H0
V_L0/R_L0
V_CC
NC
V_L3/R_L3
V_H3/R_H3
V_W3/R_W3
A₀
NC
3
FN8192.3
October 19, 2005