X40430 Datasheet, PDF (3/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430, X40431, X40434, X40435
PIN DESCRIPTION (Continued)
Pin Name
Function
5
MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t_PURST thereafter.
6 RESET/ RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
RESET ^{ever V}CC ^{falls below V}TRIP1 ^{voltage or if manual reset is asserted. This output stays active for the pro-}
grammed time period (t_PURST) on power-up. It will also stay active until manual reset is released and for
t_PURST thereafter.
RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever V_CC falls below V_TRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t_PURST) on power-up. It will also stay active until manual reset is released and for
t_PURST thereafter.
7
V_SS Ground
8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10MΩ typical).
11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the V_TRIP3 voltage, V3FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V_SS or V_CC when not used. The
V3MON comparator is supplied by the V3MON input.
12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V_TRIP3 and goes
HIGH when V3MON exceeds V_TRIP3. There is no power-up reset delay circuitry on this pin.
13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
14 V_CC Supply Voltage
PRINCIPLES OF OPERATION
Figure 1. Connecting a Manual Reset Push-Button
Power-on Reset
Applying power to the X40430, X40431, X40434,
X40435 activates a Power-on Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V_CC exceeds the device V_TRIP1 threshold value
for t_PURST (selectable) the circuit releases the RESET
(X40431, X40435) and RESET (X40430, X40434) pin
allowing the system to begin operation.
System
Reset
X40430, X40434
V_CC
RESET
MR
Manual
Reset
Manual Reset
By connecting a push-button directly from MR to ground,
the designer adds manual system reset capability. The
MR pin is LOW while the push-button is closed and
RESET/RESET pin remains HIGH/LOW until the push-
button is released and for t_PURST thereafter.
3
FN8251.0
July 29, 2005