ICL8049 Datasheet, PDF (3/3 Pages) Intersil Corporation – Antilog Amplifier

ICL8049
V+
R₃
15kΩ
V_IN
16
R₁
R₆
15.9kΩ
R₄
100kΩ
2
2kΩ
680Ω
(LOW
R₅
15kΩ
T.C.)
R₂
1kΩ
V-
1
-
A₁
+
V_REF
(+15V)
R_REF
C₁
15kΩ
I_REF
7 200pF ₃
Q₁ Q₂
+
A₂
-
14
I_OUT
R_OUT
10kΩ
10
V_OUT
15
12 ^R7 13
2kΩ
V+
FIGURE 1. ICL8049 OFFSET AND SCALE FACTOR ADJUSTMENT
ICL8049 Detailed Description
The ICL8049 relies on the same logarithmic properties of
the transistor as the ICL8048. The input voltage forces a
specific ∆V_BE between Q₁ and Q₂ (Figure 1). This V_BE
difference is converted into a difference of collector currents
by the transistor pair. The equation governing the behavior
of the transistor pair is derived from (2) on the previous page
and is as follows:
II_--CC----12--
=
exp
q_----∆_----V_---B----E--
kT
(1)
When numerical values for q/kT are put into this equation, it
is found that a ∆V_BE of 59mV (at +25^oC) is required to
change the collector current ratio by a factor of ten. But for
ease of application, it is desirable that a 1V change at the
input generate a tenfold change at the output. The required
input attenuation is achieved by the network comprising R₁
and R₂. In order that scale factors other than one decade
per volt may be selected, R₂ is external to the chip. It should
have a value of 1kΩ, adjustable ±20%, for one decade per
volt. R₁ is a thin film resistor deposited on the monolithic
chip; its temperature characteristics are chosen to
compensate the temperature dependence of Equation 1, as
explained on the previous page.
The overall transfer function is as follows:
I_{-I-OR---UE---FT-}
=
exp
(^---R^---₁^-----R+---^2--R^---₂^---)
×
q---V---I--N-
kT
(2)
Substituting V_OUT = I_OUT x R_OUT gives:
VOUT
=
ROUT
IREF exp
(^---R^----₁^-–---R+----^2-R^----₂^----)
×
q_----V_---I--N---
kT
(3)
For voltage references Equation 3 becomes
VOUT
=
VREF × -^RR---^OR---^UE---_FT- exp
(^---R^---₁^{-–---+R---2-}R^----₂^--)^-
×
q---V---I-N--
kT
(4)
ICL8049 Offset and Scale Factor
Adjustment
As with the log amplifier, the antilog amplifier requires three
adjustments. The first step is to null out the offset voltage of
A₂. This is accomplished by reverse biasing the base-emitter
of Q₂. A₂ then operates as a unity gain buffer with a
grounded input. The second step forces V_IN = 0; the output is
adjusted for V_OUT = 10V. This step essentially “anchors” one
point on the transfer function. The third step applies a
specific input and adjusts the output to the correct voltage.
This sets the scale factor. Referring to Figure 1 the exact
procedure for 1 decade/volt is as follows:
1. Connect the input (pin #16) to +15V. This reverse biases
the base-emitter of Q₂. Adjust R₇ for V_OUT = 0V. Discon-
nect the input from +15V.
2. Connect the input to Ground. Adjust R₄ for V_OUT = 10V.
Disconnect the input from Ground.
3. Connect the input to a precise 2V supply and adjust R₂ for
V_OUT = 100mV.
The procedure outlined above optimizes the performance
over a 3 decade range at the output (i.e., V_OUT from 10mV)
to 10V). For a more limited range of output voltages, for
example 1V to 10V, it would be better to use a precise 1V
supply and adjust for V_OUT = 1V. For other scale factors and/
or starting points, different values for R₂ and R_REF will be
needed, but the same basic procedure applies.
3