ICL7650-SCPD Datasheet, PDF (3/13 Pages) Intersil Corporation – 2MHz, Super Chopper-Stabilized Operational Amplifier

Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +0.3) to (V- -0.3)
Voltage on Oscillator Control Pins . . . . . . . . . . . . . . . . . . . . V+ to V-
Duration of Output Short Circuit. . . . . . . . . . . . . . . . . . . . . Indefinite
Current to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
While Operating (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .100μA
Operating Conditions
Temperature Range
ICL7650SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Thermal Information
Thermal Resistance (Typical, Note 2)
θ_JA (°C/W) θ_JC (°C/W)
8 Lead PDIP Package* . . . . . . . . . . . . 110
N/A
14 Lead PDIP Package . . . . . . . . . . . .
90
N/A
8 Lead SOIC Package . . . . . . . . . . . . . 160
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Limiting input current to 100μA is recommended to avoid latchup problems. Typically 1mA is safe, however this is not guaranteed.
2. θ_JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications V_SUPPLY = ±5V. See Test Circuit, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP.
(°C)
Input Offset Voltage (Note 3)
V_OS
+25
0 to +70
Average Temperature Coefficient of
Input Offset Voltage (Note 3)
ΔV_OS/ΔT
0 to +70
Change in Input Offset with Time
Input Bias Current |I(+)|, |I(-)|
ΔV_OS/ΔT
I_BIAS
+25
+25
0 to +70
Input Offset Current |I(-), |I(+)|
I_OS
+25
0 to +70
Input Resistance
Large Signal Voltage Gain (Note 3)
R_IN
A_VOL
R_L = 10kΩ, V_O = ±4V
+25
+25
0 to +70
Output Voltage Swing (Note 4)
V_OUT
R_L = 10kΩ
+25
R_L = 100kΩ
+25
Common Mode Voltage Range (Note 3)
CMVR
+25
0 to +70
Common Mode Rejection Ratio
(Note 3)
CMRR CMVR = -5V to +3.5V
+25
0 to +70
Power Supply Rejection Ratio
Input Noise Voltage
PSRR
V_S = ±3V to ±8V
+25
e_N
R_S = 100Ω,
+25
f = DC to 10Hz
Input Noise Current
Gain Bandwidth Product
i_N
f = 10Hz
+25
GBWP
+25
Slew Rate
Rise Time
Overshoot
SR
C_L = 50pF, R_L = 10kΩ
+25
t_R
+25
OS
+25
Operating Supply Range
V+ to V-
+25
Supply Current
I_SUPP
No Load
+25
0 to +70
MIN
TYP
MAX UNITS
-
±0.7
±5
μV
-
±1
±8
μV
-
0.02
-
μV/°C
-
100
- nV/√month
-
4
10
pA
-
5
20
pA
-
8
20
pA
-
10
40
pA
-
10¹²
-
Ω
135
150
-
dB
130
-
-
dB
±4.7 ±4.85
-
V
-
±4.95
-
V
-5 -5.2 to +4 3.5
V
-5
-
3.5
V
120
140
-
dB
120
-
-
dB
120
140
-
dB
-
2
-
μV_P-P
-
0.01
-
pA/√Hz
-
2
-
MHz
-
2.5
-
V/μs
-
0.2
-
μs
-
20
-
%
4.5
-
16
V
-
2
3
mA
-
-
3.2
mA
3
FN2920.10
April 12, 2007