HSP50016 Datasheet, PDF (3/31 Pages) Intersil Corporation – Digital Down Converter

HSP50016
Pin Description
NAME
V_CC
GND
DATA0-15
CLK
RESET
TYPE
-
-
I
I
I
I
O
Q
O
IQCLK
O
IQSTB
O
IQSTRT
I
CDATA
I
CCLK
I
CSTB
I
CS
I
TCK
I
TMS
I
TDI
I
TDO
O
TRST
I
DESCRIPTION
+5V Power.
Ground.
Input Data Bus. Selectable between two's complement and offset binary. DATA0 is the LSB.
Clock for input data bus. f_S is the frequency of CLK, which is also the input sample rate.
RESET initializes the internal state of the DDC. During RESET, all internal processing stops. RESET
facilitates the synchronization of multiple chips for Auto Three-State operation. If the Force bits in Control
Word 7 are inactive and the IEEE Test Access Port is in an Idle state, RESET causes the IQCLK, IQSTB,
I and Q outputs to go to a high impedance state.
All Control Registers are updated from their respective Control Buffer Registers on the third rising edge
of CLK after the deassertion of RESET. If RESET is deasserted t_RS nanoseconds prior to the rising edge
of CLK, the internal reset will deassert synchronously. If t_RS is violated, then the circuit contains a syn-
chronizer which will cause reset to be deasserted internally one or more clocks later.
An initial reset is required to guarantee proper operation of the DDC. Active low.
The I output has three modes: I data; I data followed by Q data; real data.
The Q output has two modes: Q data and the carry out of the Phase Adder.
IQ Clock: Bit or word clock for the I and Q outputs.
IQ Strobe: Beginning or end of word indicator for I and Q.
IQ Start: Initiates output data sequence. Active low.
Control Data: Port for control data input.
Control Data Clock: Control data input bit clock.
Control Data Strobe: Beginning of word indicator for control data.
Chip Select: Enables control data loading of DDC. Active low.
Test Clock: Bit Clock for IEEE 1149.1 Data. This signal should be either tied low or pulled high when the
TAP is not used.
Test Port Mode Select: This signal should be either left unconnected or pulled high when the TAP is not
used.
Test Data Input for IEEE Test Port: This signal should be either left unconnected or pulled high when the
TAP is not used.
Test Data Output for IEEE Test Port: This output will be in the high impedance state when the TAP is
not used.
Test Port Reset. Active Low. This signal should be tied low when the TAP is not used.
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