HI5860_14 Datasheet, PDF (3/12 Pages) Intersil Corporation – 12-Bit, 130MSPS, High Speed D/A Converter

HI5860
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1 through 12 D11 (MSB) Through Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
D0 (LSB)
13,14
NC
No Connect. (Available as 2 additional LSBs on the HI5960, 14-bit device).
15
SLEEP
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
pin has internal 20μA active pull-down current.
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AV_DD to disable internal
reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V_FSADJ/R_SET.
19
COMP1
For use in reducing bandwidth/noise. Recommended: Connect 0.1µF to AV_DD .
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP2
Connect 0.1µF capacitor to ACOM.
24
20, 25
AV_DD
ACOM
Analog Supply (+2.7V to +5.5V).
Connect to Analog Ground.
26
DCOM
Connect to Digital Ground.
27
DV_DD
Digital Supply (+2.7V to +5.5V).
28
CLK
Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is
latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes
through when the clock is logic high and is latched into the “slave” latches when the clock is logic low.
Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the
clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC
being updated on the rising clock edge. For optimum spectral performance, it is recommended that the
clock edge be skewed such that set-up time is larger than the hold time.
3
FN4654.7
February 6, 2008