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HI5812_05 Datasheet, PDF (3/16 Pages) Intersil Corporation – CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold
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HI5812
Absolute Maximum Ratings
Supply Voltage
VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V
VAA+ to VAA- . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)
VAA+ to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
Analog and Reference Inputs
VIN, VREF+, VREF- . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V)
Digital I/O Pins . . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65οC to 150oC
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF- = GND, CLK = External 750kHz,
Unless Otherwise Specified
25oC
-40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN TYP MAX
MIN
MAX
ACCURACY
Resolution
12
-
-
12
-
Integral Linearity Error, INL
J
(End Point)
K
-
-
±1.5
-
±1.5
-
-
±1.0
-
±1.0
Differential Linearity Error, DNL
J
-
-
±2.0
-
±2.0
K
-
-
±1.0
-
±1.0
Gain Error, FSE
J
(Adjustable to Zero)
K
-
-
±3.0
-
±3.0
-
-
±2.5
-
±2.5
Offset Error, VOS
J
(Adjustable to Zero)
K
-
-
±2.0
-
±2.0
-
-
±1.0
-
±1.0
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
DYNAMIC CHARACTERISTICS
VREF = 4V
VDD = VAA+ = 5V ±5%
VDD = VAA+ = 5V ±5%
-
-
±0.1 ±0.5
±0.5
±0.1 ±0.5
±0.5
Signal to Noise Ratio, SINAD
RMS Signal
J fS = Internal Clock, fIN = 1kHz
-
68.8
-
-
-
fS = 750kHz, fIN = 1kHz
69.2
RMS Noise + Distortion
K fS = Internal Clock, fIN = 1kHz
-
71.0
-
-
-
fS = 750kHz, fIN = 1kHz
71.5
Signal to Noise Ratio, SNR
RMS Signal
J fS = Internal Clock, fIN = 1kHz
-
70.5
-
-
-
fS = 750kHz, fIN = 1kHz
71.1
RMS Noise
K fS = Internal Clock, fIN = 1kHz
-
71.5
-
-
-
fS = 750kHz, fIN = 1kHz
72.1
Total Harmonic Distortion, THD
J fS = Internal Clock, fIN = 1kHz
-
-73.9
-
-
-
fS = 750kHz, fIN = 1kHz
-73.8
K fS = Internal Clock, fIN = 1kHz
-
-80.3
-
-
-
fS = 750kHz, fIN = 1kHz
-79.0
UNITS
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
dB
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
3
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