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| HI5812 Datasheet, PDF (3/13 Pages) Intersil Corporation – CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold | |||
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HI5812
Absolute Maximum Ratings
Thermal Information
Supply Voltage
VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V
VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)
VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
Analog and Reference Inputs
VIN, VREF+, VREF-. . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V)
Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V)
Operating Conditions
Temperature Range
PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . .
60
12
PDIP Package . . . . . . . . . . . . . . . . . . .
80
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65οC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in âAbsolute Maximum Ratingsâ may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this speciï¬cation is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Speciï¬cations VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF- = GND, CLK = External 750kHz,
Unless Otherwise Speciï¬ed
25oC
-40oC TO 85oC
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
(End Point)
Differential Linearity Error, DNL
Gain Error, FSE
(Adjustable to Zero)
Offset Error, VOS
(Adjustable to Zero)
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
Total Harmonic Distortion, THD
Spurious Free Dynamic Range,
SFDR
TEST CONDITIONS
MIN TYP MAX MIN
J
K
J
K
J
K
J
K
VREF = 4V
VDD = VAA+ = 5V ±5%
VDD = VAA+ = 5V ±5%
12
-
-
12
-
-
±1.5
-
-
-
±1.0
-
-
-
±2.0
-
-
-
±1.0
-
-
-
±3.0
-
-
-
±2.5
-
-
-
±2.0
-
-
-
±1.0
-
0.1 ±0.5
0.1 ±0.5
J fS = Internal Clock, fIN = 1kHz
-
68.8
-
-
fS = 750kHz, fIN = 1kHz
69.2
K fS = Internal Clock, fIN = 1kHz
-
71.0
-
-
fS = 750kHz, fIN = 1kHz
71.5
J fS = Internal Clock, fIN = 1kHz
-
70.5
-
-
fS = 750kHz, fIN = 1kHz
71.1
K fS = Internal Clock, fIN = 1kHz
-
71.5
-
-
fS = 750kHz, fIN = 1kHz
72.1
J fS = Internal Clock, fIN = 1kHz
-
-73.9
-
-
fS = 750kHz, fIN = 1kHz
-73.8
K fS = Internal Clock, fIN = 1kHz
fS = 750kHz, fIN = 1kHz
-80.3 -
-
-79.0
J fS =Internal Clock, fIN = 1kHz
- -75.4 -
-
fS = 750kHz, fIN = 1kHz
-75.1
K fS = Internal Clock, fIN = 1kHz
-
-80.9
-
-
fS = 750kHz, fIN = 1kHz
-79.6
MAX UNITS
-
Bits
±1.5
LSB
±1.0
LSB
±2.0
LSB
±1.0
LSB
±3.0
LSB
±2.5
LSB
±2.0
LSB
±1.0
LSB
±0.5
LSB
±0.5
LSB
-
dB
dB
-
dB
dB
-
dB
dB
-
dB
dB
-
dBc
dBc
-
dBc
dBc
-
dB
dB
-
dB
dB
6-1791
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