HD6408_15 Datasheet, PDF (3/12 Pages) Intersil Corporation – CMOS Asynchronous Serial Manchester Adapter

Pin Description
PIN
TYPE
1
O
2
O
SYMBOL
VW
ESC
3
O
TD
4
O
5
I
SDO
DC
6
I
7
I
8
I
9
O
10
O
BZI
BOI
UDI
DSC
CDS
11
I
12
I
13
I
14
O
15
O
16
I
17
O
18
I
19
I
20
I
21
O
22
I
23
I
24
I
DR
GND
MR
DBS
BZO
OI
BOO
SDI
EE
SS
SD
SCI
EC
V_CC
HD-6408
SECTION
Decoder
Encoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Both
Both
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Both
DESCRIPTION
Output high indicates receipt of a VALID WORD.
ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The
Encoder samples SDI on the low-to-high transition of ESC.
TAKE DATA output is high during receipt of data after identification of a sync pulse
and two valid Manchester data bits.
SERIAL DATA OUT delivers received data in correct NRZ format.
DECODER CLOCK input drives the transition finder, and the synchronizer which in
turn supplies the clock to the balance of the Decoder. Input a frequency equal to
12X the data rate.
A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative
state. This pin must be held high when the Unipolar input is used.
A high input should be applied to BIPOLAR ONE IN when the bus is in its positive
state, this pin must be held low when the Unipolar input is used.
With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition
finder circuit. If not used this input must be held low.
DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ³ 12),
synchronized by the recovered serial data stream.
COMMAND/DATA SYNC output high occurs during output of decoded data which
was preceded by a Command synchronizing character. A low output indicates a
Data synchronizing character.
A high input to DECODER RESET during a rising edge of DECODER SHIFT
CLOCK resets the decoder bit counting logic to a condition ready for a new word.
GROUND supply pin.
A high on MASTER RESET clears the 2:1 counters in both the encoder and
decoder and the ³  6 counter.
DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER
CLOCK.
BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative
sense of a bipolar line driver.
A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.
BIPOLAR ONE OUT is an active low output designed to drive the one or positive
sense of a bipolar line driver.
SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER
SHIFT CLOCK.
A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preceding
cycle being completed).
SYNC SELECT actuates a Command sync for an input high and data sync for an
input low.
SEND DATA is an active high output which enables the external source of serial
data.
SEND CLOCK IN is 2X the Encoder data rate.
ENCODER CLOCK is the input to the 6:1 divider.
V_CC is the +5V power supply pin. A 0.1µF decoupling capacitor from V_CC (pin 24)
to GND (pin 12) is recommended.
3
FN2952.3
October 1, 2015