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DG506A_07 Datasheet, PDF (3/19 Pages) Intersil Corporation – CMOS Analog Multiplexers
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DG506A, DG507A, DG508A, DG509A
Functional Diagrams
DG506A
S1
S2
S3
S4
S5
S6
S7
S8
D
S9
S10
S11
S12
S13
S14
ADDRESS DECODER
1 OF 16
S15
S16
A0 A1 A2 A3
ENABLE
1 OF 4
EN
4 Line Binary Address Inputs
(0 0 0 1) and EN = 5V
Above example shows channel 2 turned ON.
DG508A
S1
S2
S3
S4
D
S5
ADDRESS DECODER
S6
1 OF 8
S7
S8
A0 A1 A2 EN (ENABLE INPUT)
3 Line Binary Address Inputs
(1 0 1) and EN = 1
Above example shows channel 6 turned ON.
DG507A
S1A
S2A
S3A
S4A
DA
S5A
S6A
S7A
S8A
S1B
S2B
S3B
S4B
DB
S5B
ADDRESS DECODER ENABLE
S6B
1 OF 8
1 OF 2
S7B
S8B
A0 A1 A2 EN (ENABLE INPUT)
3 Line Binary Address Inputs
(0 0 0) and EN = 5V
Above example shows channels 1A and 1B turned ON.
DG509A
S1A
S2A
S3A
DA
S4A
S1B
S2B
DB
S3B
S4B
2 Line Binary Address Inputs
(0 0) and EN = 1
Above example shows channels 1A and 1B turned ON.
Schematic Diagram
V+
LOGIC TRIP
POINT REF
GND
LOGIC AX
INPUT OR EN
V-
LOGIC INTERFACE
AND LEVEL SHIFTER
DECODER
+
-
AX
V+
SX
DX
TYPICAL
SWITCH
3
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