CA3224E_02 Datasheet, PDF (3/6 Pages) Intersil Corporation – Automatic Picture Tube Bias Control Circuit

CA3224E
Test Circuit
1
V_IN1
2
V_IN2
3
0.047
µF
4
+10V
V_BIAS
3.65K
22
B
21
S₁
A ^0.12µF
20
V_OUT1
B _3.65K
19
S₁ ^{A 0.12µF}
V_IN3
0.047
µF
5
18
6
17
CA3224E
V_OUT2
B _3.65K
S₁ ^{A 0.12µF}
VERTICAL
INPUT
7
0.047
µF 8
9
16
47µF
15
+
V_OUT3
+20V
14
3.32K
HORIZONTAL
INPUT
1.50K
1.0K
+10V
B
10
13
20K
S₂ ^A
11
12
1.5K
Device Description and Operation (See Figures
1, 2, 4 and 5)
During the vertical retrace interval, 13 horizontal sync pulses
are counted. On the 14th sync pulse the auto-bias pulse
output goes high. This is used to set the RGB drive of the
companion chroma/luma circuit to black level. The auto-bias
pulse stays high for 7 horizontal periods during the auto-bias
cycle.
On the 15th horizontal sync pulse, the internal logic initiates the
setup interval. During the setup interval, the cathode current is
increased to a reference value (A in Figure 5) through the
action of the grid pulse. The cathode current causes a voltage
drop across R_S. This voltage drop, together with the program
pulse output results in a reference voltage at V_S (summing
point) which causes capacitor C₁ to charge to a voltage
proportional to the reference cathode current. The setup
interval lasts for 3 horizontal periods.
On the 18th horizontal sync pulse the grid pulse output
goes high, which through the grid pulse amplifier/inverter,
causes the cathode current to decrease. The decrease in
cathode current results in a positive recovered voltage
pulse with respect to the setup reference level at the VS
summing point. The positive recovered voltage pulse is
summed with a negative voltage pulse caused by the
program pulse output going low (cutting off Diode D1 and
switching in resistors R1 and R2). Any difference between
the positive and negative pulses is fed through capacitor
C1 to the transconductance amplifier. The difference signal
is amplified in the transconductance amplifier and charges
the hold capacitor C2, which, through the buffer amplifier,
adjusts the bias on the driver circuit.
Components RS, R1, and R2 must be chosen such that the
program pulse and the recovered pulse just cancel at the
desired cathode cutoff level.
CHAN FREQ
HOLD CHAN CHAN FREQ
1 IN COMP CAPACITOR 1 OUT 2 IN COMP
23
21
20
4
5
HOLD
CAPACITOR
19
CHAN CHAN FREQ
2 OUT 3 IN COMP
18
6
7
HOLD
CAPACITOR
17
CHAN
3 OUT
16
AMPLIFER
NO. 1
1
-
2
+
3
g_M
BUFFER
AMP
x1
AMPLIFER
NO. 2
1
-
2
+
g_M
3
BUFFER
AMP
x1
AMPLIFER
NO. 3
1
-
2
+
g_M
3
BUFFER
AMP
x1
V_REF
MODE
SWITCH
BIAS
LOGIC
1
GND
MODE SWITCH
1
2
3
9
GND
STATE
SET-UP
SENSE
OPEN
3
22
V_CC
15
V_REF
BYPASS
8
VERT
IN
10
HORIZ
IN
11
GRID
PULSE
OUT
12
PROG
PULSE
OUT
13
AUTO
BIAS
PULSE
OUT
14
AUTO
BIAS
LEVEL
ADJUST
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM