ISL6334D_14 Datasheet, PDF (27/28 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Phase Dropping, Droop Disabled and Load Current Monitoring Features

ISL6334D
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space between
the components is minimized while creating the PHASE
plane. Place the Intersil MOSFET driver IC as close as
possible to the MOSFETs they control to reduce the parasitic
impedances due to trace length between critical driver input
and output signals. If possible, duplicate the same placement
of these components for each phase.
Next, place the input and output capacitors. Position one high
frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to the
upper MOSFET drains, as dictated by the component size
and dimensions. Long distances between input capacitors
and MOSFET drains result in too much trace inductance and
a reduction in capacitor performance. Locate the output
capacitors between the inductors and the load, while keeping
them in close proximity to the microprocessor socket.
Voltage-Regulator (VR) Design Materials
The tolerance band calculation (TOB) worksheets for VR
output regulation and IMON have been developed using the
Root-Sum-Squared (RSS) method with 3 sigma distribution
point of the related components and parameters. Note that
the “Electrical Specifications” table beginning on page 6
specifies no less than 6 sigma distribution point, not suitable
for RSS TOB calculation. Intersil also developed a set of
worksheets to support VR design and layout. Contact
Intersil’s local office or field support for the latest available
information.
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FN6802.3
November 22, 2013