ISL6266 Datasheet, PDF (27/31 Pages) Intersil Corporation – Precision Two/One-phase CORE Voltage Regulator

ISL6266, ISL6266A
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, the ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user is
strongly encouraged to use the evaluation board values and
layout to minimize engineering time.
The 2.1mV/A load line should be adjusted by R_drp2 based
on maximum current. The droop gain might vary slightly
between small steps (e.g. 10A). For example, if the max
current is 40A and the load line 2.1mthe user load the
converter to 40A and look for 84mV of droop. If the droop
voltage is less than 84mV (e.g. 80mV) the new value will be
calculated by Equation 30:
R_drp2-new = ⁸⁸----⁴⁰----^mm-----^VV-- R_drp1 + R_drp2 – R_drp1
(EQ. 30)
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the previous example, the resistance on the DFB pin is
R_drp1 in parallel with R_drp2, that is, 1k in parallel with
5.82k or 853. The resistance on the VSUM pin is R_n in
parallel with RS_EQV or 5.87k in parallel with 1.825k,
which equals 1392. The mismatch in the effective
resistances is 1404 - 53 = 551. The mismatch cannot be
larger than 600. To reduce the mismatch, multiply both
R_drp1 and R_drp2 by the appropriate factor. The appropriate
factor in this example is 1404/853 = 1.65. In summary, the
predicted load line with the designed droop network
parameters based on the Intersil design tool is shown in
Figure 41.
2.25
2.20
2.15
2.10
2.05
0
20
40
60
80
100
INDUCTOR TEMPERATURE (°C)
FIGURE 41. LOAD LINE PERFORMANCE WITH NTC
THERMAL COMPENSATION
Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value, which could be
problematic if a load dump were to occur during this time.
This situation would cause the output voltage to rise above
the no load setpoint of the converter and could potentially
damage the CPU.
The L/DCR time constant of the inductor must be matched to
the R_n*C_n time constant as shown in Equation 31.
D^-----C^-L----R^{--- =} R^-R----_nn^{-----+----RR-----SS----EE----QQ----V-}_V^{--  Cn}
(EQ. 31)
Solving for C_n we now have Equation 32.
C_n = --_RR--------_n-_{n---------+}--^D----------_R-_R----^C-L--------_S^-_S-----^R-------_E-_E-------QQ---------_V-V----
(EQ. 32)
Note, R_O was neglected. As long as the inductor time
constant matches the C_n, R_n and R_s time constants as given
previously, the transient performance will be optimum. As in
the static droop case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
example of L = 0.36µH with 0.8m DCR, C_n is calculated in
Equation 33.
C_n = _p----_a----_r---_a---_l--_l--_e----_l--_-^0--₅^-0-----^..--.-3-₈^-0-----^{62--0------}₃₀^-------_K8-^H------_,---₁----_.-₈----₂---₅---_K-----_  330nF
(EQ. 33)
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this capacitor
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip lower than the voltage required by the load line and
slowly increases back to steady state, the capacitor is too
small and vice versa. It is better to have the capacitor value
a little bigger to cover the tolerance of the inductor to prevent
the output voltage from going lower than the spec. This
capacitor needs to be a high grade capacitor like X7R with
low tolerance. There is another consideration in order to
achieve better time constant match mentioned previously.
The NPO/COG (class-I) capacitors have only 5% tolerance
and very good thermal characteristics. However, these
capacitors are only available in small capacitance values. In
order to use such capacitors, the resistors and thermistors
surrounding the droop voltage sensing and droop amplifier
has to be resized up to 10x larger to reduce the capacitance
by 10x. Careful attention must be paid in balancing the
impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.1mV/A load line, the impedance
needs to be 2.1m. The compensation design has to target
the output impedance of the converter to be 2.1m. There is
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FN6398.4
August 25, 2015