ISL51002_07 Datasheet, PDF (27/32 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
channel may look like SOG activity when there actually is no
SOG signal, while non-standard SOG signals and TriLevel
sync signals may have amplitudes below the default SOG
slicer levels and not be easily detected. As a consequence,
not all of the activity detect bits in the ISL51002 are correct
under all conditions.
For best SOG operation, the SOG low pass filter (register
0x04[4] should always be enabled to reject the high
frequency peaking often seen on video signals.
HSYNC and VSYNC Activity Detect
Activity on these bits always indicates valid sync pulses, so
they should have the highest priority and be used even if the
SOG activity bit is also set.
SOG Activity Detect
The SOG activity detect bit monitors the output of the SOG
slicer, looking for 64 consecutive pulses with the same
period and duty cycle. If there is no signal on the Green
(or Y) Channel, the SOG slicer will clamp the video to a DC
level and will reject any sporadic noise. There should be no
false positive SOG detects if there is no video on Green
(or Y) Channel.
If there is video on Green (or Y) Channel with no valid SOG
signal, the SOG activity detect bit may sometimes report
false positives (it will detect SOG when no SOG is actually
present). This is due to the presence of video with a
repetitive pattern that creates a waveform similar to SOG.
For example, the desktop of a PC operating system is black
during the front porch, horizontal sync, and back porch, then
increases to a larger value for the video portion of the
screen. This creates a repetitive video waveform very similar
to SOG that may falsely trigger the SOG Activity detect bit.
However, in these cases where there is active video without
SOG, the SYNC information will be provided either as
separate H and V sync on HSYNC_IN and VSYNC_IN, or
composite sync on HSYNC_IN. HSYNC_IN and VSYNC_IN
should therefore be used to qualify SOG. The SOG Active bit
should only be considered valid if HSYNC Activity
Detect = 0. Note: Some pattern generators can output
HSYNC and SOG simultaneously, in which case both the
HSYNC and the SOG activity bits will be set, and valid. Even
in this case, however, the monitor should still choose
HSYNC over SOG.
TriLevel Sync Detect
The TriLevel detect for Sync on Green (SOG) utilizes the
digitized data from the selected Green video channel. If
TriLevel Sync is present, the default DC Clamp start position
will clamp at the top of the TriLevel Sync pulse giving a false
negative for TriLevel detect and clamping off the bottom half
of the green video. If you have an indication of active SOG
you must move the clamp start to a value greater than 0x30
to check to see if the TriLevel Sync is present.
SYNC Output Signals
The ISL51002 has a pair of HSYNC output signals,
HSYNC_OUT and VSYNC_OUT, and HS_OUT.
HSYNC_OUT and VSYNC_OUT are buffered versions of the
incoming sync signals; no synchronization is done. These
signals are used for mode detection
HS_OUT is generated by the ISL51002’s logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. HS_OUT is used to signal the
start of a new line of digital data.
Both HSYNC_OUT and VSYNC_OUT (including the sync
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
ISL51002.
HSYNC_OUT
HSYNC_OUT is an unmodified, buffered version of the incoming
HSYNC_IN or SOG_IN signal of the selected channel, with the
incoming signal’s period, polarity, and width to aid in mode
detection. HSYNC_OUT will be the same format as the incoming
sync signal: either horizontal or composite sync. If a SOG input
is selected, HSYNC_OUT will output the entire SOG signal,
including the VSYNC portion, pre-/post-equalization pulses if
present, and Macrovision pulses if present. HSYNC_OUT
remains active when the ISL51002 is in power-down mode.
HSYNC_OUT is generally used for mode detection.
VSYNC_OUT
VSYNC_OUT is an unmodified, buffered version of the incoming
VSYNC_IN signal of the selected channel, with the original
VSYNC period, polarity, and width to aid in mode detection. If a
SOG input is selected, this signal will output the VSYNC signal
extracted by the ISL51002’s sync slicer. Extracted VSYNC will
be the width of the embedded VSYNC pulse plus pre- and post-
equalization pulses (if present). Macrovision pulses from an
NTSC DVD source will lengthen the width of the VSYNC pulse.
Macrovision pulses from other sources (PAL DVD or videotape)
may appear as a second VSYNC pulse encompassing the
width of the Macrovision. See the Macrovision section for more
information. VSYNC_OUT (including the sync separator function)
remains active in power-down mode. VSYNC_OUT is generally
used for mode detection, start of field detection, and even/odd
field detection.
HS_OUT
HS_OUT is generated by the ISL51002’s control logic and is
synchronized to the output DATACLK and the digital pixel data
on the output databus. Its trailing edge is aligned with pixel 0. Its
width, in units of pixels, is determined by register 0x2A, and its
polarity is determined by register 0x29[3]. As the width is
increased, the trailing edge stays aligned with pixel 0, while the
leading edge is moved backwards in time relative to pixel 0.
HS_OUT is used by the scaler to signal the start of a new line of
pixels.
27
FN6164.2
September 19, 2007