ZL2005 Datasheet, PDF (26/39 Pages) Intersil Corporation – Digital-DC™ Integrated Power Management and Conversion IC

ZL2005
Once the sensing method has been selected, the user
must select the voltage threshold (V_LIM) based on
equation 26, the desired current limit threshold, and
the resistance of the sensing element.
The current limit threshold can be selected by simply
connecting the ILIM0 and ILIM1 pins as shown in
Table 19. The ground-referenced sensing method is
being used in this mode.
Table 19. Current Limit Threshold Voltage Settings
ILIM0
LOW OPEN HIGH
ILIM1
LOW
OPEN
HIGH
20 mV
50 mV
80 mV
30 mV
60 mV
90 mV
40 mV
70 mV
100 mV
The threshold voltage can also be selected in 5 mV
increments by connecting a resistor, R_LIM0, between
the ILIM0 pin and ground according to Table 20. This
method is preferred if the user does not desire to use or
does not have access to the I²C/SMBus interface and
the desired threshold value is contained in Table 20.
Table 20. Current Limit Threshold Voltage Settings
V_LIM
0 mV
R_LIM0
10 kΩ
V_LIM
55 mV
R_LIM0
28.7 kΩ
5 mV
11 kΩ
60 mV _{31.6 kΩ}
10 mV _{12.1 kΩ}
65 mV _{34.8 kΩ}
15 mV _{13.3 kΩ}
70 mV _{38.3 kΩ}
20 mV _{14.7 kΩ}
75 mV _{42.2 kΩ}
25 mV _{16.2 kΩ}
80 mV _{46.4 kΩ}
30 mV _{17.8 kΩ}
85 mV _{51.1 kΩ}
35 mV _{19.6 kΩ}
90 mV _{56.2 kΩ}
40 mV _{21.5 kΩ}
95 mV _{61.9 kΩ}
45 mV _{23.7 kΩ}
100 mV _{68.1 kΩ}
50 mV _{26.1 kΩ}
The current limit threshold can be set via the I²C/
SMBus interface. Please refer to Application Note
AN13 for further details on setting current limit
parameters.
5.10 Loop Compensation
The ZL2005 operates as a voltage-mode synchronous
buck controller with a fixed frequency PWM scheme.
Although the ZL2005 uses a digital control loop, it
operates much like a traditional analog PWM control-
ler. See Figure 15 for a simplified block diagram of the
ZL2005 control loop, which differs from an analog
control loop by the constants in the PWM and com-
pensation blocks. As in the analog controller case, the
compensation block compares the output voltage to
the desired voltage reference and compensation zeros
are added to keep the loop stable. The resulting inte-
grated error signal is used to drive the PWM logic,
converting the error signal into a duty cycle value to
drive the external MOSFETs.
V_IN
D
DPWM
1-D
L
C _RO
R_C
V_OUT
Compensation
Figure 15. Control Loop Block Diagram
In the ZL2005, the compensation zeros are set by con-
figuring the FC0 and FC1 pins or via the I²C/SMBus
interface once the user has calculated the required set-
tings. This method eliminates the inaccuracies due to
the component tolerances associated with using exter-
nal resistors and capacitors. Most applications can be
served by using the pin-strap compensation settings
listed in Table 21. These settings will yield a conserva-
tive crossover frequency at a fixed fraction of the
switching frequency (f_Sw/20) and 60° of phase margin.
26
FN6848.0
February 18, 2009