ISLA110P50 Datasheet, PDF (26/35 Pages) Intersil Corporation – 10-Bit, 500MSPS A/D Converter

ISLA110P50
value + hysteresis to again enter the Track state. The
hysteresis quantity is a 24-bit value, constructed with bits
23 through 12 (MSBs) being assigned to 0, bits 11 through
4 assigned to this register’s value, and bits 3 through 0
(LSBs) assigned to 0.
ADDRESS 0X60-0X64: I2E INITIALIZATION
These registers provide access to the initialization values
for each of offset, gain, and sample time skew that I2E
programs into the target core A/D before adjusting to
minimize interleave mismatch. They can be used by the
system to, for example, reduce the convergence time of
the I2E algorithm by programming in the optimal values
before turning I2E on. In this case, I2E only needs to
adjust for temperature and voltage-induced changes
since the optimal values were recorded.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing
skew between the two A/D cores. The nominal range and
resolution of this adjustment are given in Table 10. The
default value of this register after power-up is 80h.
TABLE 10. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the
A/D input sample clock. Some systems with multiple
A/Ds can more easily latch the data from each A/D by
controlling the phase of the output data clock. This
control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output
data clock to be advanced by one input clock period, as
shown in the Figure 44. Execution of a phase_slip
command is accomplished by first writing a '0' to bit 0 at
address 0x71, followed by writing a '1' to bit 0 at address
0x71.
ADC Input
Clock (500MHz)
2ns
4ns
Output Data
Clock (250MHz)
No clock_slip
2ns
Output Data
Clock (250MHz)
1 clock_slip
Output Data
Clock (250MHz)
2 clock_slip
FIGURE 44. PHASE SLIP
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
ISLA110P50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 17). This functionality can be overridden and
controlled through the SPI, as shown in Table 11.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to
“Data Format” on page 18). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12.
This register is not changed by a Soft Reset.
TABLE 11. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
OUTPUT MODE
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 12. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default)
or slow.
Internal clock signals are generated by a delay-locked
loop (DLL), which has a finite operating range. Table 13
shows the allowable sample rate ranges for the slow and
fast settings.
DLL RANGE
Slow
Fast
TABLE 13. DLL RANGES
MIN
MAX
80
200
160
500
UNIT
MSPS
MSPS
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock generator. The method
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FN7606.1
June 4, 2010