ISL12028_1011 Datasheet, PDF (26/29 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12028, ISL12028A
.
V_DD
V_BAT(3.0V)
V_RESET(2.63V)
V_TRIP
(2.2V)
tPURST
RESET
I²C-BUS ACTIVE
I_BAT
(V_DD POWER, V_BAT NOT CONNECTED)
(BATTERY BACKUP MODE)
FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C
V_DD
V_BAT (3.0V)
V_RESET (2.63V)
V_TRIP
(2.2V)
t_PURST
RESET
I²C-BUS ACTIVE
I_BAT
(BATTERY BACKUP MODE)
FIGURE 30. RESET OPERATION IN MODE D
Alarm Operation Examples
Following, are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm 0 set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm 0 registers as follows:
BIT
ALARM0
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
MOA0 1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week
disabled
B. Also the AL0E bit must be set as follows:
BIT
ALARM0
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
DTA0
1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
BIT
CONTROL
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
INT
0 0 1 0 0 0 0 0 x0h Enable Alarm
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/F_OUT output
low.
26
FN8233.9
November 30, 2010