ISL97674_10 Datasheet, PDF (24/28 Pages) Intersil Corporation – 6-Channel LED Driver with Phase Shift Control and Frame Rate to Dimming Frequency Synchronization

ISL97674
REGISTER 0x0B
PLL CONTROL REGISTER
PLLDivBy4 PLLDivide6 PLLDivide5 PLLDivide4 PLLDivide3 PLLDivide2 PLLDivide1 PLLDivide0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
PLLDivBy4
PLLDivide[6..0]
BIT FIELD DEFINITIONS
PLL input frequency range control bit.
Controls PLL divide setting:
If PLLDivBy4 = 0, Freq(PWM) = Freq(Vsync) * (1 + PLLDivide)/5
If PLLDivBy4 = 1, Freq(PWM) = 4 * Freq(Vsync) * (1 + PLLDivide)/5
FIGURE 38. DESCRIPTIONS OF PLL CONTROL REGISTER
Phase Shift Control Register (0x0A)
The Phase Shift Control register is used to set phase
delay between each channels. When bit 7 is set high, the
phase delay is set by the number of channels enabled
and the PWM frequency. The delay time is defined by the
Equation 12:
t_DELAY = (t_FPWM ⁄ N)
(EQ. 12)
where N is the number of channels enabled, and t_FPWM is
the period of the PWM cycle. When bit 7 is set low, the
phase delay is set by bits 6 to 0 and the PWM frequency.
The delay time is defined by Equation 13:
t_DELAY = (PS < 6, 0 > xt_FPWM ⁄ (255))
(EQ. 13)
where PS is an integer from 0 to 127, and t_FPWM is the
period of the PWM cycle. By default, all the register bits
are set low, which sets zero delay between each channel.
Note that the user should not program the register to
give more than one period of the PWM cycle delay
between the first and last enabled channels.
PLL Control Register (0x0B)
The PLL Control register is used to set up the PLL. The
PWM frequency generated by the PLL is defined by
Equation 14:
f_PWM
=
⎛
⎝
f_VSY
N
C^x
(_---P_----L_----L_----D_---5--I_--V_-----+-----1_----)⎠⎞
(EQ. 14)
where PLLDIVBY4 = 0
f_PWM
=
⎛
⎝
4
x
f_V
S
Y
N
C
x
(_---P_----L_----L_----D_---5--I_--V_-----+-----1_----)⎠⎞
(EQ. 15)
where PLLDIVBY4 =1
where f_VSYNC is the frequency of the incoming signal on
PLLDIV is an integer from 0 to 127. For incoming
frequencies less than 40Hz, the PLLDIVBY4 bit should be
set high. The default setting for this register is 0x10,
which gives a generated PWM frequency of 204 Hz with
an incoming frame rate of 60Hz.
Components Selections
According to the inductor Voltage-Second Balance
principle, the change of inductor current during the
switching regulator On time is equal to the change of
inductor current during the switching regulator Off time.
Since the voltage across an inductor is:
V_L = L × ΔI_L ⁄ Δt
(EQ. 16)
and ΔI_L @ On = ΔI_L @ Off, therefore:
(V_I – 0 ) ⁄ L × D × t_S= (V_O – V_D – V_I) ⁄ L × (1 – D ) × t_S
(EQ. 17)
where D is the switching duty cycle defined by the
turn-on time over the switching period. V_D is Schottky
diode forward voltage that can be neglected for
approximation.
Rearranging the terms without accounting for V_D gives
the boost ratio and duty cycle respectively as
Equations 18 and 19:
V_O ⁄ V_I = 1 ⁄ (1 – D)
(EQ. 18)
D = (V_O – V_I ) ⁄ V_O
(EQ. 19)
Input Capacitor
Switching regulators require input capacitors to deliver
peak charging current and to reduce the impedance of
the input supply. This reduces interaction between the
regulator and input supply, thereby improving system
stability. The high switching frequency of the loop causes
almost all ripple current to flow in the input capacitor,
which must be rated accordingly.
A capacitor with low internal series resistance should be
chosen to minimize heating effects and improve system
efficiency, such as X5R or X7R ceramic capacitors, which
offer small size and a lower value of temperature and
voltage coefficient compared to other ceramic capacitors.
In Boost mode, input current flows continuously into the
inductor; AC ripple component is only proportional to the
rate of the inductor charging, thus, smaller value input
capacitors may be used. It is recommended that an input
capacitor of at least 10µF be used. Ensure the voltage
24
FN7634.0
June 25, 2010