ISL28117_14 Datasheet, PDF (23/34 Pages) Intersil Corporation – 40V Precision Low Power Operational Amplifiers

ISL28117, ISL28217, ISL28417
*ISL28117 Macromodel - covers following
*products
*ISL28117
*ISL28217
*ISL28417
**Revision History:
*Revision C, LaFontaine January 31, 2012
*Model for Noise, quiescent supply currents,
*CMRR 210dB, fcm=10Hz, AVOL 155dB
*f=0.02Hz, SR = 0.5V/us, output voltage
*clamp and short ckt current limit.
*
*Copyright 2012 by Intersil Corporation Refer
*to data sheet "LICENSE STATEMENT", Use
*of this model indicates your acceptance with
*the terms and provisions in the License
*Statement.
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
**
*Device performance features supported by
*this model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
:
*
+input
*
| -input
*
| | +Vsupply
*
| | | -Vsupply
*
| | | | output
*
| ||| |
.subckt ISL28117 Vin+ Vin- V+ V- VOUT
* source ISL28107subckt
*
*Voltage Noise
E_En IN+ VIN+ 25 0 1
R_R17 25 0 290
D_D12 24 25 DN
V_V7 24 0 0.1
*
*Input Stage
I_IOS IN+ VIN- DC 0.08E-9
C_C6 IN+ VIN- 1.2E-12
R_R1 VCM VIN- 5e11
R_R2 IN+ VCM 5e11
Q_Q1 2 VIN- 1 SuperB
Q_Q2 3 8 1 SuperB
Q_Q3 V-- 1 7 Mirror
Q_Q4 4 6 2 Cascode
Q_Q5 5 6 3 Cascode
R_R3 4 V++ 4.45e3
R_R4 5 V++ 4.45e3
C_C4 VIN- 0 2e-12
C_C5 8 0 2e-12
D_D1 6 7 DX
I_IEE 1 V-- DC 200e-6
I_IEE1 V++ 6 DC 96e-6
V_VOS 9 IN+ 8e-6
E_EOS 8 9 VC VMID 1
*
*1st Gain Stage
G_G1 V++ 11 4 5 8.129384e-2
G_G2 V-- 11 4 5 8.129384e-2
R_R5 11 V++ 1
R_R6 V-- 11 1
D_D2 10 V++ DX
D_D3 V-- 12 DX
V_V1 10 11 1.86
V_V2 11 12 1.86
*
*2nd Gain Stage
G_G3 V++ VG 11 VMID 2.83e-3
G_G4 V-- VG 11 VMID 2.83e-3
R_R7 VG V++ 1.99e10
R_R8 V-- VG 1.99e10
C_C2 VG V++ 4e-10
C_C3 V-- VG 4e-10
D_D4 13 V++ DX
D_D5 V-- 14 DX
V_V3 13 VG 1.86
V_V4 VG 14 1.86
*
*Mid supply Ref
R_R9 VMID V++ 2.1E3
R_R10 V-- VMID 2.1E3
I_ISY V+ V- DC 0.44E-3
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
*
*Common Mode Gain Stage with Zero
G_G5 V++ VC VCM VMID 3.162277
G_G6 V-- VC VCM VMID 3.162277
R_R11 VC 17 1
R_R12 18 VC 1
L_L1 17 V++ 15.9159E-3
L_L2 18 V-- 15.9159E-3
FIGURE 57. SPICE NET LIST
*
*Output Stage with Correction Current
Sources
G_G7 VOUT V++ V++ VG 1.11e-2
G_G8 V-- VOUT VG V-- 1.11e-2
G_G9 22 V-- VOUT VG 1.11e-2
G_G10 23 V-- VG VOUT 1.11e-2
D_D6 VG 20 DX
D_D7 21 VG DX
D_D8 V++ 22 DX
D_D9 V++ 23 DX
D_D10 V-- 22 DY
D_D11 V-- 23 DY
V_V5 20 VOUT 1.12
V_V6 VOUT 21 1.12
R_R15 VOUT V++ 9E1
R_R16 V-- VOUT 9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3
+rb=140 re=0.011 rc=900 cje=0.2E-12
+cjc=0.16E-12f kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12
+cjc=0.44E-12 kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28117
23
November 30, 2012
FN6632.10