KAD5610P Datasheet, PDF (22/27 Pages) List of Unclassifed Manufacturers – Dual 10-Bit, 250/210/170/125MSPS A/D Converter

KAD5610P
DLL RANGE
Slow
Fast
TABLE 15. DLL RANGES
MIN
MAX
40
100
80
f_S MAX
UNIT
MSPS
MSPS
The output_mode_B and config_status registers are used in
conjunction to select the frequency range of the DLL clock
generator. The method of setting these options is different
from the other registers.
READ
OUTPUT_MODE_B
0x74
READ
CONFIG_STATUS
0x75
DESIRED
VALUE
WRITE TO
0x74
FIGURE 40. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in
Figure 40. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with the
desired value for output_mode_B and write that XOR result
to the register.
Device Test
The KAD5610 can produce preset or user defined patterns
on the digital outputs to facilitate in-situ testing. A static word
can be placed on the output bus, or two different words can
alternate. In the alternate mode, the values defined as Word
1 and Word 2 (as shown in Table 16) are set on the output
bus on alternating clock phases. The test mode is enabled
asynchronously to the sample clock, therefore several
sample clock cycles may elapse before the data is present
on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to Table 17.
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
TABLE 16. OUTPUT TEST MODES
0xC0[3:0]
OUTPUT TEST
MODE
WORD 1
Off
Midscale
0x8000
Positive Full-Scale 0xFFFF
Negative Full-Scale 0x0000
Checkerboard
0xAAAA
Reserved
N/A
Reserved
N/A
One/Zero
0xFFFF
User Pattern
user_patt1
WORD 2
N/A
N/A
N/A
0x5555
N/A
N/A
0x0000
user_patt2
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
22
FN6810.1
January 30, 2009