KAD5512P-50 Datasheet, PDF (22/26 Pages) List of Unclassifed Manufacturers – 12-Bit, 500MSPS A/D Converter

KAD5512P-50
SPI Memory Map
TABLE 17. SPI MEMORY MAP
Addr
(Hex)
00
01
02
03-07
08
09
10
11-1F
20
21
22
23
24
25
26-5F
60-6F
70
71
72
73
74
Parameter Name Bit 7 (MSB) Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
port_config
reserved
burst_end
reserved
chip_id
chip_version
device_ ind ex _A
reserved
offset_coarse
offset_fine
gain_coarse
gain _m ed iu m
gain_fine
modes
reserved
reserved
skew_diff
phase_slip
clock _d ivide
outp ut_ mode_A
outp ut_ mode_B
SDO Active
LSB First
Soft Reset
Reserved
Burst end address [7:0]
Reserved
Chip ID #
Chip Version #
Reserved
Reserved
Reserved
Coarse Offset
Fine Offset
Medium Gain
Fine Gain
Reserved
Reserved
Different ial Skew
Reserved
Output Mode [2:0]
000=Pin Control
001=LVDS 2mA
010=LVDS 3mA
100=LV CMOS
other codes=reserved
DLL Range
0=fast
1=slow
Mirror (bit5) Mirror (bit6)
ADC 01
Coarse Gain
Power Down Mode [2:0]
000=Pin Control
001=Normal Operation
010=Nap
100=Sleep
other codes=reserved
Clock Divide [2:0]
000=Pin Control
001=divide by 1
010=divide by 2
100=divide by 4
other codes=reserved
Output Format [2:0]
000=Pin Control
001=Twos Complement
010=Gray Code
100=Offset Binary
other codes=reserved
Mirror (bit7)
ADC00
Next Clock
Edge
Def. Value Indexed/
(Hex) Global
00h G
00h G
Read only G
Read only G
00h I
cal. value I
cal. value I
cal. value I
cal. value I
cal. value I
00h I
NOT
affected by
Soft Reset
80h G
00h G
00h G
NOT
affected by
Soft Reset
00h G
NOT
affected by
Soft Reset
00h G
NOT
affected by
Soft Reset
75
76-BF
C0
config_status
reserved
test _io
XOR Result
Read Only G
Reserved
User Test M ode [2:0]
Reset PN Reset PN
Output Test Mode [3:0]
00h G
00=Single
01=Alt ernate
10=Single Once
11=Alt ernate Once
Long Gen
Short Gen
0=Off
1=Midscale Short
2=+FS Short
3=- FS Short
7=One/Zero Word Togg le
8=User Input
9-15=reserved
4=Checker Board
5=reserved
6=reserved
C1
Reserved
Reserved
C2
user_patt 1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
C3
user_patt 1_msb B15
B14
B 13
B12
B11
B10
B9
B8
C4
user_patt 2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
C5
user_patt 2_msb B15
B14
B 13
B12
B11
B10
B9
B8
C6-FF reserved
Reserved
00h G
00h G
00h G
00h G
00h G
22
FN6805.0
December 5, 2008