ISL95820 Datasheet, PDF (22/47 Pages) Intersil Corporation – Green Hybrid Digital Four Phase PWM Controller for Intel VR12.5 CPUs

ISL95820
Inductor Current Sensing and Balancing
INDUCTOR DCR CURRENT-SENSING NETWORK
PHASE1 PHASE2 PHASE3
Rsum
Rsum
Rsum
ISUMP
L
L
L
DCR
DCR
DCR
Rntcs
Rp
Rntc
Ro
Ro
Ro
Cn Vcn
Ri ^ISUMN
Io
FIGURE 18. DCR CURRENT-SENSING NETWORK
Figure 18 shows the inductor DCR current-sensing network for the
example of a 3-phase voltage regulator. An inductor’s current flows
through the inductor’s DCR and creates a voltage drop. Each
inductor has two resistors, R_sum and R_o, connected to the pads to
accurately sense the inductor current by sensing the DCR voltage
drop. The R_sum and R_o resistors are connected in a summing
network as shown, and feed the total current information to the
NTC network (consisting of R_ntcs, R_ntc and R_p) and capacitor C_n.
R_ntc is a negative temperature coefficient (NTC) thermistor, used
to compensate for the change in inductor DCR due to temperature
changes.
The inductor output side pads are electrically shorted in the
schematic, but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10Ω R_o to create quality signals. Since the R_o value is much
smaller than the rest of the current sensing circuit, the following
analysis will ignore it for simplicity.
The summed inductor current information is presented to the
capacitor C_n. Equations 24 thru 28 describe the
frequency-domain relationship between inductor total current
I_o(s) and C_n voltage V_Cn(s):
⎛
⎞
V_Cn(s)
=
⎜
⎜
⎜
⎝
-----------^R-----ⁿ---^t--^c---ⁿ----^e---^t-----------
R_n
t
cn
e
t
+
-^R----^s---^u---^m---
N
×
D_-----CN_-----R_{---⎟⎟⎟}
⎠
× I_o(s) × A_cs(s)
(EQ. 24)
R_ntcnet
=
(_---R_{-----n---t--c---s----+-----}R_{----n----t--c---})_---×_-----R_----p--
R_ntcs + R_ntc + R_p
A_cs(s)
=
----¹----+------^ω-----^s----L-----
1 + -_ω----_s-^s--_n---_s-
(EQ. 25)
(EQ. 26)
ω_L
=
D_-----C_-----R_---
L
(EQ. 27)
ω_sns
=
---------------------------¹-----------------------------
-^R----ⁿ---^t--^c---ⁿ----^e---^t---^×------^R--------^s--^N----^u-------^m------
R_ntcnet
+
-^R----^s---^u---^m---
N
×
C_n
(EQ. 28)
where N is the number of phases.
The inductor DCR value increases as the inductor temperature
increases, due to the positive temperature coefficient of the
copper windings. If uncompensated, this will cause the estimate
of inductor current to increase with temperature. The resistance
of the co-located NTC thermistor, R_ntc, decreases as its
temperature increases, compensating for the increase in DCR.
Proper selections of R_sum, R_ntcs, R_p and R_ntc parameters ensure
that V_Cn represents the inductor total DC current over the
temperature range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC network
and the R_sum resistors form a voltage divider, V_cn is always a
fraction of the inductor DCR voltage. It is recommended to have a
high ratio of V_cn to the inductor DCR voltage, so the current sense
circuit has a higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R_sum = 3.65kΩ, R_p = 11kΩ, R_ntcs = 2.61kΩ
and R_ntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
V_Cn(s) response must track I_o(s) over a broad range of frequency
for the controller to achieve good transient response. Transfer
function A_cs(s) (Equation 29) has unity gain at DC, a pole ω_sns,
and a zero ω_L. To obtain unity gain at all frequencies, set ω_L
equal to ω_sns and solve for Cn.
C_n
=
------------------------------^L--------------------------------
-^R----ⁿ---^t--^c---ⁿ----^e---^t---^×------^R--------^s--^N----^u-------^m------
R_ntc
n
e
t
+
-^R----^s---^u---^m---
N
×
D
C
R
(EQ. 29)
For example, given N = 3, R_sum = 3.65kΩ, R_p = 11kΩ,
R_ntcs = 2.61kΩ, R_ntc = 10kΩ, DCR = 0.9mΩ and L = 0.36µH,
Equation 29 gives C_n = 0.397µF.
Assuming the loop compensator design is correct, Figure 26
shows the expected load transient response waveforms for the
correctly chosen value of C_n. When the load current I_core has a
step change, the output voltage V_core also has a step change,
determined by the DC loadline resistance (the output voltage
droop value of the regulator, (see “Current Sense Circuit
22
FN8318.0
February 4, 2013