ISL62881 Datasheet, PDF (22/35 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62881, ISL62881B
Optional Slew Rate Compensation Circuit
For 1-Tick VID Transition
Rdroop
R_vid Cvid
FB
Ivid
Vcore
OPTIONAL
Idroop_vid
COMP
E/A
Σ
DAC
VDAC
X1
INTERNAL TO
IC
VIDs
VID<0:6>
RTN
VSS
VSSSENSE
VID<0:6>
Vfb
Ivid
Vcore
Idroop_vid
FIGURE 23. OPTIONAL SLEW RATE COMPENSATION
CIRCUIT FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the
VIDs at a controlled slew rate of 2.5µs or 1.25µs per tick
(12.5mV), controlling output voltage V_core slew rate at
5mV/µs or 10mV/µs.
Figure 23 shows the waveforms of 1-tick VID transition.
During 1-tick VID transition, the DAC output changes at
approximately 15mV/µs slew rate, but the DAC cannot
step through multiple VIDs to control the slew rate.
Instead, the control loop response speed determines
V_core slew rate. Ideally, V_core will follow the FB pin
voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
I_{droop_vid} waveform shows, and will droop the output
voltage V_core accordingly, making V_core slew rate slow.
Similar behavior occurs during the down transition.
To control V_core slew rate during 1-tick VID transition,
one can add the R_vid-C_vid branch, whose current I_vid
cancels I_{droop_vid}.
When V_core increases, the time domain expression of the
induced I_droop change is as shown in Equation 31:
I_droop(t)
=
-^C----^o---^u----^t---^×----^L----^L--
R_droop
×
-^d---^V-----^c---^o---^r--^e-
dt
×
⎛
⎜⎜ ¹
⎝
–
e ^{-C----o----u---–-t--t-×-----L---L--}_{⎟⎟⎞}
⎠
(EQ. 31)
where C_out is the total output capacitance.
In the meantime, the R_vid-C_vid branch current I_vid time
domain expression is as shown in Equation 32:
I_vid(t)
=
C_vid
×
d_----V_-----f-b--
dt
×
⎛
⎜
⎜
1
–
e
R^-----_v^----_i^-_d^----–-×^---t--C^-----_v^---_i^--_d^--_⎟⎞
⎟
⎝
⎠
(EQ. 32)
It is desired to let I_vid(t) cancel I_{droop_vid}(t). So there
are:
C_vid
×
d_----V_-----f-b--
dt
=
-^C----^o---^u----^t---^×-----^L---^L--
R_droop
×
-^d---^V-----^c---^o---^r--^e-
dt
(EQ. 33)
and:
R_vid × C_vid = C_out × LL
(EQ. 34)
The result is:
R_vid = R_droop
(EQ. 35)
and:
C_vid
=
C_{-----o---u----t---}×_----L_----L_--
×
-^d---^V-----^c---^o---^r--^e-
--------^d---^t--------
R_droop
d_----V_-----f-b--
dt
(EQ. 36)
For example: given LL = 3mΩ, R_droop = 4.22kΩ,
C_out = 1320µF, dV_core/dt = 5mV/µs and
dV_fb/dt = 15mV/µs, Equation 35 gives R_vid = 4.22kΩ
and Equation 36 gives C_vid = 227pF.
It’s recommended to select the calculated R_vid value and
start with the calculated C_vid value and tweak it on the
actual board to get the best performance.
During normal transient response, the FB pin voltage is
held constant, therefore is virtual ground in small signal
sense. The R_vid-C_vid network is between the virtual
ground and the real ground, and hence has no effect on
transient response.
Voltage Regulator Thermal Throttling
Figure 24 shows the thermal throttling feature with
hysteresis. An NTC network is connected between the
NTC pin and GND. At low temperature, SW1 is on and
SW2 connects to the 1.20V side. The total current
flowing out of the NTC pin is 60µA. The voltage on NTC
pin is higher than the threshold voltage of 1.20V and the
comparator output is low. VR_TT# is pulled up by the
external resistor.
22
FN6924.0
October 26, 2009