ISL28127_1012 Datasheet, PDF (22/26 Pages) Intersil Corporation – Precision Single and Dual Low Noise Operational Amplifiers

ISL28127, ISL28227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev. (Continued)
REVISION
DATE
CHANGE
FN6633.3
(Continued)
3/2/10
In “Absolute Maximum Ratings” on page 4, HBM for ISL28227 changed from “4kV” to “6kV”
In “Thermal Information” on page 4, Tjc values for ISL28227 changed:
For MSOP from “50” to “45”
For SOIC from “60” to “55”
2/25/10
In the “Ordering Information” (page 2):
Part Number
Part Marking
ISL28127FRTBZ
ISL28127FRTZ -C 127Z instead of 127Z C
ISL28127FUBZ
ISL28127FUZ 8127Z -C instead of 8127Z
Removed “Coming Soon) for ISL28127FUZ package
ISL28227FBZ
Removed “Coming Soon) for ISL28227FBZ package
ISL28227FRTBZ
ISL28227FRTZ -C 227Z instead of 227Z C
ISL28227FUZ
8227Z -C instead of 8227Z
Vos (Max) (uV)
TBD instead of 70
TBD instead of 70
150 instead of 70
80 instead of 70
TBD instead of 70
150 instead of 70
Added the following row of data
ISL28227FUBZ
8227Z
TBD
In the “Electrical specifications” on page 4 and page 6 the following changes were made. The change applies to the same
spec found on page 4 and page 6.
FN6633.2
VOS Offset Voltage; SOIC Package, ISL28127: Added -70 to MIN across room temp and -120 MIN across full temp
VOS Offset Voltage; SOIC Package, ISL28227: Added -80 to MIN across room temp and -160 MIN across full temp
VOS Offset Voltage; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -150 to MIN across room temp and -
250 MIN across full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28127: Added -0.5 to MIN across full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28227: Added -0.8 to MIN across full temp
TCVOS Offset Voltage Drift; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -1 to MIN across full temp
IOS Input Offset Current: Added -10 to MIN across room temp and -12 to MIN across full temp
IB Input Bias Current:Added -10 to MIN across room temp and -12 to MIN across full temp
2/19/10 In the “Ordering Information” (page 2), added differentiated part numbers for B-grade and C-grade for TDFN and MSOP.
In “Absolute Maximum Ratings” on page 4, added ESD and latch-up information.
In “Thermal Information” on page 4, broke out Theta JA to list the single and dual and added Theta JC.
1/29/10
Added license statement for P-Spice Model.
Updated Spice Schematic by adding capacitors
C4, C5 and C6
Updated Spice Net List as follows:
From:
Revision B, July 23 2009
To:
Revision C, August 8th 2009 LaFontaine
From:
source ISL28127_SPICEMODEL_7_9
To:
source ISL28127_SPICEMODEL_0_0
Added after I_IOS:
C_C6 IN+ VIN- 2E-12
Added after R_R4:
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
From:
.ends ISL28127
To:
.ends ISL28127subckt
Replaced POD MDP0027 with M8.15E to match ASYD in Intrepid (no dimension changes; the PODs are the same. The
change was to update to the Intersil format, moving dimensions from table onto drawing and adding land pattern)
22
FN6633.6
December 16, 2010