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ISL28108_1111 Datasheet, PDF (22/32 Pages) Intersil Corporation – 40V Precision Single Supply Rail-Rail Output Low Power Operational Amplifiers
Vin-
Vin+
0.1
V7 1
D13 D14
0
1150 2
0
GAIN = 0.3
I2
6E-6
V++
I1
12e-6
9
I3
6E-6
R2
5
R1
5e11
CinDif
1.21e-12
PNP_LATERAL
IOS
3e-9
7 Q7
Q8
PNP_input
D1DBREAK
Q6 10 PNP_LATERAL
D2DBREAK
Q9
12
PNP_input
8
R3
6250
6
11
R4
6250
Cin2
Cin1
V--
4.19e-12
4.19e-12
V++
D3
G1
+-
13
R5 1
GAIN = 0.477
-6.74 V1
EOS
-++-
E
GAIN = 1
14
Vc
Vmid
-6.76 V2
15 G2 R6 1
GAIN = 0.477
D4
V--
Input Stage
1st Gain Stage
V+
E2
+- +-
0 GAIN = 1
V++
V++
G3
+
-
Vmid
GAIN = 261.74e-6
-6.74
-6.76
G4 Vmid
GAIN = 261.74e-6
D5
16
C1
R7 2.31e-11
7.62e9
V3
R19
R13
L1
L3
1.59E-08
1.59E-08
G5
G7
+-
18 +-
21
GAIN = 0.6 R9 GAIN = 0.6
3.183e3
G15
G9
3.183e3
+-
+-
GAIN = 314.15e-6 GAIN = 314.15e-6
D7
1e-3
R11
C5
C3
24
19
1e-3
10e-12
10e-12 DX
D10
D11
Vg
Vc
28
23
26
27
Vmid
ISY
185e-6
C6
E4
10e-12
V4
++
--
GAIN = 0.5
17
C2
R10
1e-3
20
R12
1e-3
22
G16
C4
G10
10e-12
R8 2.31e-11
7.62e9
G6
GAIN = 0.6
G8
L2
1.59E-08
GAIN = 0.6
L4
GAIN = 314.15e-6 GAIN = 314.15e-6
1.59E-08
R20
R14
3.183e3
3.183e3
D8 25
G11
G12
+-
+-
D12
D9 GAIN = 12.5e-3
GAIN = 12.5e-3
V--
V--
V5
-0.4
V6
-0.4
2nd Gain Stage
Mid Supply ref V
Common Mode
Gain Stage
with Zero
V- E3
++
--
GAIN = 1
0
FIGURE 67. SPICE MODEL SCHEMATIC
Output Stage Correction Current Sources
G13
R15
GAIN = 12.5e-3 80
VOUT
G14
R16
80
GAIN = 12.5e-3