HFA3842 Datasheet, PDF (22/26 Pages) Intersil Corporation – Wireless LAN Medium Access Controller

HFA3842
TABLE 9. BBP TRANSMIT PORT AC ELECTRICAL
SPECIFICATIONS (Continued)
PARAMETER
SYMBOL MIN MAX
UNITS
TXRDY Inactive To
Last Chip of MPDU
Out
t_RI
-20 20 ns
TXD Modulation
Extension
t_ME
2
- µs (Note 19)
NOTES:
18. I_OUT/Q_OUT are modulated before first valid chip of preamble is
output to provide ramp up time for RF/IF circuits.
19. TX_PE must be inactive before going active to generate a new
packet.
20. I_OUT/Q_OUT are modulated after last chip of valid data to provide
ramp down time for RF/IF circuits.
21. Delay from TXC to inactive edge of TXPE to prevent next TXC.
Because TXPE asynchronously stops TXC, TXPE going inactive
within 40ns of TXC will cause TXC minimum hi time to be less
than 40ns.
TXC
TX_PE
FIRST DATA BIT SAMPLED
LAST DATA BIT SAMPLED
TXD
TXRDY
LSB DATA PACKET
MSB
DEASSERTED WHEN LAST
CHIP OF MPDU CLEARS
MOD PATH OF 3861
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXC.
FIGURE 23. BBP TRANSMIT PORT TIMING
TX_PE
t_DI
I_OUT, Q_OUT
TXRDY
TXC
TXD
t_PEH
t_{TCD tTCD}
t_RC
t_TLP
t_ME
t_RI
t_TDS
t_TDH
FIGURE 24. BBP TRANSMIT PORT SIGNAL TIMING
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