ISLA214P50 Datasheet, PDF (21/39 Pages) Intersil Corporation – 14-Bit, 500MSPS ADC

ISLA214P50
experiment to determine if performance degradation is
observed.
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 25.
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the ISLA214P50 is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to less than 104mW while Sleep mode reduces power
dissipation to less than 19mW.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 500MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 25.
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can also be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 25.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
BINARY
13 12 11 • • • •
10
••••
GRAY CODE
13 12 11
•••• 1 0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
GRAY CODE
13 12 11 • • • •
1
0
••••
••••
BINARY
13 12 11
•••• 1 0
Mapping of the input voltage to the various data formats is
shown in Table 3.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale 00 0000 0000
0000
10 0000 0000
0000
00 0000 0000
0000
–Full Scale 00 0000 0000
+ 1LSB
0001
10 0000 0000
0001
00 0000 0000
0001
Mid–Scale 10 0000 0000
0000
00 0000 0000
0000
11 0000 0000
0000
+Full Scale 11 1111 1111
– 1LSB
1110
01 1111 1111
1110
10 0000 0000
0001
+Full Scale 11 1111 1111
1111
01 1111 1111
1111
10 0000 0000
0000
21
FN7571.2
December 10, 2012