ISL85033 Datasheet, PDF (21/25 Pages) Intersil Corporation – Wide VIN Dual Standard Buck Regulator With 3A/3A Coutinuous Output Current

ISL85033
Vo
R₂
C₃
V _{FB -}
V _COMP
R₃
V _REF
GM
+
R₁
C₂
C₁
FIGURE 47. TYPE II COMPENSATOR
Figure 47 shows the type II compensator and its transfer
function is expressed as Equation 22:
A_v(S)=
-^vˆ---c_vˆ---^oF---^m-_B----^p- =
-------^g----^m---------
C₁ + C₂
-^⎝⎛--¹-----+------^ω--------^c-^S-----z-------^{1---⎠⎞}----^⎝⎛--¹-----+------^ω---------^{cS------z------2----⎠⎞}-
S_⎝⎛1 + _ω----^S-_c---_p-_⎠⎞
(EQ. 22)
Where:
ω_cz1
=
-------¹-------
R₁C₁
,
ω_cz2
=
-_R----₂--¹-_C-----₃-, ω_cp=
--^C----¹-----+----^C-----²--
R₁C₁C₂
(EQ. 23)
the compensator design goal is:
High DC gain
Loop bandwidth f_c:
⎛
⎝
1_--
4
t
o
1^--1--0^{--⎠⎞}
f_s
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is shown in
Equation 24:
Put compensator zero
ω_cz1
=
(
1t
o
3
)
--------¹---------
R_OC_O
(EQ. 24)
Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at
either ESR zero frequency or half switching frequency,
whichever is lower.
The loop gain T_v(S) at crossover frequency of f_c has unity
gain. Therefore, the compensator resistance R₁ is
determined by Equation 25:
R₁
=
2_----π_----f_--c---V_----o----C_----o----R_----T--
g_mV_FB
(EQ. 25)
where g_m is the trans-conductance of the voltage error
amplifier, typically 200uA/V. Compensator capacitor C₁ is
then given by Equation 26:
C₁
=
--------¹---------
R₁ω_cz
,C₂ =
------------¹------------
2πR₁f_esr
(EQ. 26)
Example: V_IN = 12V, V_o = 5V, I_o = 3A, f_s = 500kHz,
C_o = 220µF/5mΩ, L = 5.6µH, g_m = 200µs, R_T = 0.21,
V_FB = 0.8V, S_e = 1.1×10⁵V/s, S_n = 3.4×10⁵V/s,
f_c = 80kHz, then compensator resistance R₁ = 72kΩ.
Put the compensator zero at 6.6kHz (~1.5x C_oR_o), and
put the compensator pole at ESR zero, which is
1.45MHz. The compensator capacitors are:
C₁ = 470pF, C₂ = 3pF (There is approximately 3pF
parasitic capacitance from V_COMP to GND; therefore,
C₂ is optional).
Figure 48A shows the simulated voltage loop gain. It is
shown that it has 80kHz loop bandwidth with 69° phase
margin and 15dB gain margin. Optional addition phase
boost can be added to the overall loop response by
using C₃.
60
45
30
GAIN (dB)
15
0
-15
-30
100
1•10³
1•10⁴
1•10⁵
FIGURE 48A.
1•10⁶
100
80
60
PHASE (°)
40
20
0
-20
100
1•10³
1•10⁴
1•10⁵
FIGURE 48B.
1•10⁶
Rectifier Selection
Current circulates from ground to the junction of the
external Schottky diode and the inductor when the high-
side switch is off. As a consequence, the polarity of the
switching node is negative with respect to ground. This
voltage is approximately -0.5V (a Schottky diode drop)
during the off-time. The rectifier's rated reverse
breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating
factor. The power dissipation when the Schottky diode
conducts is expressed in Equation 27:
P_D[W]
=
I_OUT
⋅
V_D
⋅
⎛
⎜
⎝
1
–
V_{----V-O---I-U-N---T--⎠⎟⎞}
(EQ. 27)
21
FN6676.1
June 24, 2010