ISL59532_07 Datasheet, PDF (21/24 Pages) Intersil Corporation – 32x32 Video Crosspoint

ISL59532
For this reason, the ISL59532 must be in DC-coupled
mode (Clamp Disabled) to be compatible with s-video
and component video signals.
Bandwidth Considerations
Wide frequency response (high bandwidth) in a video
system means better video resolution. Four sets of
frequency response curves are shown in Figure 47.
Depending on the switch configurations, and the routing (the
path from the input to the output), bandwidth can vary
between 100MHz and 350MHz. A short discussion of the
trade-offs — including matrix configuration, output buffer
gain selection, channel selection, and loading — follows.
2
MUX, A_V = 2
0
BROADCAST,
-2
A_V = 1
MUX, A_V = 1
-4
BROADCAST,
A_V = 2
-6
-8
-10
1
10
100
FREQUENCY (MHz)
1000
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES
In multiplexer mode, one input typically drives one output
channel, while in broadcast mode, one input drives all 32
outputs. As the number of outputs driven increases, the
parasitic loading on that input increases. Broadcast Mode is
the worst-case, where the capacitance of all 32 channels
loads one input, reducing the overall bandwidth. In addition,
due to internal device compensation, an output buffer gain of
x2 has higher bandwidth than a gain of x1. Therefore, the
highest bandwidth configuration is multiplexer mode (with
each input mapped to only one output) and an output buffer
gain of x2.
The relative locations of the input and output channels also
have significant impact on the device bandwidth (due to the
layout of the ISL59530 silicon). When the input and output
channels are further away, there are additional parasitics as
a result of the additional routing, resulting in lower
bandwidth.
The bandwidth does not change significantly with resistive
loading as shown in the typical performance curves.
However several of the curves demonstrate that frequency
response is sensitive to capacitance loading. This is most
significant when laying out the PCB. If the PCB trace length
between the output of the crosspoint switch and the back-
termination resistor is not minimized, the additional parasitic
capacitance will result in some peaking and eventually a
reduction in overall bandwidth.
Linear Operating Region
In addition to bandwidth optimization, to get the best linearity
the ISL59532 should be configured to operate in its most
linear operating region. Figure 48 shows the differential gain
curve. The ISL59532 is a single supply 5V design with its
most linear region between 0.1 and 2V. This range is fine for
most video signals whose nominal signal amplitude is 1V.
The most negative input level (the sync tip for composite
video) should be maintained at 0.3V or above for best
operation.
FIGURE 48. DIFFERENTIAL GAIN RESPONSE
In a DC-coupled application, it is the system designer’s
responsibility to ensure that the video signal is always in the
optimum range.
When AC coupling, the ISL59532’s Clamp (also called “DC
restore”) function automatically and continuously adjusts the
DC level so that the most negative portion of the video is
always equal to V_REF.
A discussion of the benefits of the DC restoration function
begins by understanding the Clamp circuit shown in
Figure 49. The incoming video signal is typically terminated
into 75Ω, then AC coupled through C₁, at which point it is
connected to the base of the buffer’s diff pair. These
components form the video path.
The Clamp function consists of Q₁, D₁, Q₂, D₂, the two
current sources, and the 3 switches controlled by the Clamp
Enable signal. The V_REF voltage is level-shifted up two
diode drops (Q₁ and D₁) to the base of Q₂. If the voltage at
the cathode of D₂ goes below V_REF, Q₂ and D₂ will turn on,
keeping the IN_x voltage at V_REF. If the voltage at IN_x is
greater than V_REF, Q₂ and D₂ are off and the IN_x node is
high impedance. This is how the clamp function forces the
lowest portion of the video signal (the sync tip) to always be
equal to or greater than V_REF.
To make sure that the sync tip is always equal to (not equal
to or greater than) V_REF, i₁ is constantly sinking ~2µA of
current from C₁. This causes each sync tip to be slightly
lower voltage than the previous sync tip, causing Q₂ and D₂
to turn on at each sync tip and raise the voltage to V_REF. The
2µA pulldown with a 0.1uF capacitor and a 15kHz HSYNC
frequency results in 1.3mV of “droop” across every line, or
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FN7432.5
February 7, 2007