ISL5585_04 Datasheet, PDF (21/24 Pages) Intersil Corporation – 3.3V Ringing SLIC Family for Voice Over Broadband (VOB)

ISL5585
switch is designed to have a maximum on voltage of 0.6V
with a load current of 45mA.
+V
RELAY
SW+
SW-
SWC
FIGURE 15. EXTERNAL RELAY SWITCHING
Since the device provides the ringing waveform, the relay
functions which may be supported include subscriber
disconnect, test access or line interface bypass. An external
snubber diode is not required when using the uncommitted
switch as a relay driver.
Test Load
The switch may be used to connect test loads across Tip and
Ring. The test loads can provide external test termination for
the device. Proper connection of the uncommitted switch to
Tip and Ring is shown below.
TIP
RING
TEST
LOADSW+
SW-
SWC
FIGURE 16. TEST LOAD SWITCHING
The diode in series with the test load blocks current from
flowing through the uncommitted switch when the polarity of
the Tip and Ring terminals are reversed. In addition to the
reverse active state, the polarity of Tip and Ring are reversed
for half of the ringing cycle. With independent logic control
and the blocking diode, the uncommitted switch may be
continuously connected to the Tip and Ring terminals.
TABLE 2. ISL5585 3V APPLICATION CIRCUIT COMPONENTS
COMPONENT
VALUE
TOL RATING
U1 - Ringing SLIC
ISL5585
N/A
N/A
R_TL
18.7kΩ
1%
0.1W
R_RT
23.7kΩ
1%
0.1W
R_SH
49.9kΩ
1%
0.1W
R_IL
71.5kΩ
1%
0.1W
R_S
66.5kΩ
1%
0.1W
R_F
30.1kΩ
1%
0.1W
R_A
36.5kΩ
1%
0.1W
R_B
42.2KkΩ
1%
0.1W
R_IN
45.3kΩ
1%
0.1W
C_RS, C_TX, C_RT, C_POL
0.47µF
20%
10V
C_DC, C_FB
4.7µF
20%
6.3V
C_PS1
0.1µF
20%
>100V
C_PS2, C_PS3
0.1µF
20%
100V
D₁
1N400X type with breakdown > 100V.
R_P1, R_P2
Standard applications will use ≥ 49Ω per side. Protection resistor
values are application dependent and will be determined by
protection requirements.
Design Parameters: Ring Trip Threshold = 76mA_PEAK, Switch Hook
Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device
Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω protection
resistors, impedance across Tip and Ring terminals = 599Ω.
Transient current limit = 95mA.
Special Considerations for the QFN
Package
The new Quad Flatpack No-lead (QFN) package offers a
significant footprint reduction (65%) and improved thermal
performance with respect to the 28 lead PLCC. To realize the
thermal enhancements and maintain the high voltage
(-100V) performance, the exposed pad on the bottom of the
QFN package should be soldered to a power/heat sink plane
that is electrically connected to the ISL5585 Substrate
Common Connection (SCC) pin. The heat is distributed
evenly across the board by way of the heat sink plane. This
is accomplished by using conductive thermal vias.
Reference technical brief TB379 and AN9922 for additional
information on thermal characterization and board layout
considerations.
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