HSP50216_07 Datasheet, PDF (21/58 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

HSP50216
Single FIR Basic Program
This is the basic program for a single FIR. This program applies to decimation filters (including DECx1) that are symmetric or
asymmetric (but not complex). The FIR output is routed through path A with the AGC enabled.
0 - WAIT FOR ENOUGH SAMPLES
0000 0000 0000 0000 0000 0000 0000 0000 127:96 00000000h
0000 0000 0000 0000 0000 0000 0000 0000 95:64 00000000h
0000 0000 0000 0000 0000 0000 0000 0000 64:32 00000000h
0000 0000 0000 0000 0000 0000 0000 0001 31:0 00000001h
1 - FIR
0000 0001 0101 1111 1111 100R RRRR RRRR 127:96 015FF---h
00TT TTTT TTTD DDDD DDDD 0000 0000 0111 95:64 -----007h
0000 1000 0000 0000 0000 1010 0000 0000 63:32 08000A00h
0000 1011 0000 0000 0FFF FFF0 1100 1000 31:0 0B00--C8h
2 - JUMP TO STEP 0
0000 0000 0000 0000 0000 0000 0000 0000 127:96 00000000h
0000 0000 0000 0000 0000 0000 0000 0000 95:64 00000000h
0000 0000 0000 0000 0000 0000 0000 0000 64:32 00000000h
0000 0000 0000 0000 0000 0001 0000 0111 31:0 00000107h
Four bit fields must be filled in:
F - filter type (this example applies to types 1-5)
D - decimation (also loaded into wait threshold)
T - number of taps minus 1
R - clocks/calculation (= floor((taps+1)/2) for symmetric, = taps for asymmetric)
The rest of the instruction RAM would typically be filled with NOP instructions:
0000 0000 0000 0000 0000 0000 0000 0000 127:96 00000000h
0000 0000 0000 0000 0000 0000 0000 0000 95:64 00000000h
0000 0000 0000 0000 0000 0000 0000 0000 64:32 00000000h
0000 0000 0000 0000 0000 0000 1000 0000 31:0 00000080h
Wait Preload Register
This register (IWA register *00Ch) holds the wait counter
threshold and two wait counter decrement values. Each is
10 bits. The wait counter counts filter input samples until the
count is greater than or equal to the threshold. The wait
counter then asserts a flag to the filter compute engine.
The wait counter threshold is typically set to the total number
of input samples needed to generate a filter output. A “WAIT”
instruction in the filter compute engine waits for the wait
counter flag signal before proceeding. The filter compute
engine would then compute all the filters needed to produce
an output and then would jump back to the “WAIT”
instruction.
The wait counter is implemented with an accumulator. This
allows the count to go beyond the threshold without losing
the sample count. Two bits in the FIR instruction decrement
the wait counter (subtract a value) and select the decrement
value. The decrement value is typically the number of
samples needed for an output (total decimation), though it
can be a different value to ignore inputs and shift the timing.
(The read pointer increment must be adjusted as well.)
The filter compute engine sequencer does not count each
input sample or track whether each filter is ready to run.
Instead, the wait counter is used to determine whether there
are enough input samples to compute all the filters in the
chain and get an output sample from the entire filter chain.
This adds some additional delay since intermediate results
are not precalculated, but it simplifies the filter control. The
number of samples needed is equal to the total decimation
of the filter chain. For example, with two decimate-by-2
halfband filters and a decimate-by-2 shaping FIR, the total
decimation would be 8 so 8 samples are needed to compute
an output. HBF1 would compute four times to generate four
inputs to HBF2. HBF2 would compute twice to generate the
two samples that the shaping FIR needs to compute an
output.
21
FN4557.6
August 17, 2007