ISLA216S_14 Datasheet, PDF (20/34 Pages) Intersil Corporation – 16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC

ISLA216S
Time alignment of multiple devices provides the capability to
align samples from multiple JESD204 ADC devices in the system
in a pipeline-depth correct manner, thus enabling the system to
analyze the ADC data from multiple devices while eliminating the
variable latency of the JESD204 link as a concern. This capability
enables configurations of JESD204 ADCs as IQ, interleave,
and/or simultaneously-sampled converters.
This ADC family uses the asserted to de-asserted SYNC~
transition as the absolute time event with which to generate a
known sequence of characters at the JESD204 transmitter of
equal pipeline depth between all ADC devices in the system to be
time aligned. This is consistent with the JESD204 rev B
subclass 2 device definition.
Test Patterns
The complexity of the JESD204 interface merits much more test
pattern capability than less complex parallel interfaces. This
device family consequently supports a much wider range of test
patterns than previous ADC families.
Supported test patterns include both transport and link layer
patterns. Transport layer patterns are passed through the
transport layer of the JESD204 transmitter, following the same
sequence of being packed and sliced into octets as the ADC
sample data. Link layer test patterns bypass the transport layer
and are injected directly into the 8b/10b encoder, serialized, and
sent out of the physical media. Test pattern generation is
controlled through SPI register 0xC0.
Link layer PRBS patterns are standard PRBS patterns that can be
used with built-in standard PRBS checkers in, for example, FPGA
SERDES-capable pins.
All transport layer test patterns re-initialize their phase when the
SYNC~ de-assertion occurs; consequently, a system that provides
a well-timed SYNC~ signal with respect to the ADC sample clock
can expect transport layer test patterns to have consistent phase
with respect to that de-assertion, which can be a significant aid
when debugging the system.
TABLE 4. JESD204 PARAMETERS
PRODUCT
NUMBER JESD204
OF LANES PARAMETER ENCODED
JESD204 PARAMETERS AND FRAME MAP (Notes 16, 17, 18)
ISLA216S25
2
CF = 0
0
ISLA216S20
ISLA216S13
CS = 0
0
F=2
1
C0S0[15:8]
C0S0[7:0]
HD = 0
0
L=2
1
C0S1[15:8]
C0S1[8:0]
M=1
0
N = 16
15
N' = 16
15
S=2
1
K >= 9
>= 8
NOTES:
16. The JESD204 parameters are shown as their actual values, with the JESD204 encoded values (i.e., the values that are programmed into the SPI
registers) in the next column over. Typically values that must always be greater than 1 are encoded as value minus 1, and so on.
17. Frame map format decoder: "CxSy[a:b]" = Converter x, Sample y, bits a through b. For example, "C0S0[13:6]" = Converter 0, Sample 0, bits 13 through
6, etc. "T" = Tail bit (information-less bit packed in the transport layer mapping to form octets).
18. The topmost lane in the graphical frame map is Lane0, followed by Lane1.
20
FN7996.1
April 19, 2013